Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system

International audienceThis paper presents a new constraint-driven method for computational pattern selection, mapping and application scheduling using reconfigurable processor extensions. The presented method is a part of DURASE system (Generic Environment for Design and Utilization of Reconfigurable Application-Specific Processors Extensions). The selected processor extensions are implemented as specialized processor instructions. They correspond to computational patterns identified as most frequently occurring or other interesting patterns in the application graph. Our methods can handle both time-constrained and resource-constrained scheduling. Experimental results obtained for the MediaBench and MiBench benchmarks show that the presented method ensures high speed-ups in application execution

Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture

International audienceThis article presents an integrated environment for application scheduling, binding and routing used for the run-time reconfigurable, operator based, ROMA multimedia architecture. The environment is very flexible and after a minor modification can support other reconfigurable architectures. Currently, it supports the architecture model composed of a bank of single (double) port memories, two communication networks (with different topologies) and a set of run-time functionally reconfigurable non-pipelined and pipelined operators. The main novelty of this work is simultaneous solving of the scheduling, binding and routing tasks. This frequently generates optimal results, which has been shown by extensive experiments using the constraint programming paradigm. In order to show flexibility of our environment, we have used it in this article for optimization of application scheduling, binding and routing (the case of the non-pipelined execution model) and for space exploration (case of the pipelined execution model)

Sélection automatique d'instructions et ordonnancement d'applications basés sur la programmation par contraintes

National audienceCe papier présente une nouvelle méthode, basée sur la programmation par contraintes, pour la sélection de motifs de calcul, le placement et l'ordonnancement d'applications sur des extensions de processeurs configurables. Cette méthode est intégrée dans l'environnement DURASE (Generic Environment for Design and Utilization of Reconfigurable Application-Specific Processors Extensions). Les extensions du proces- seur, qui mettent en œuvre les motifs de calcul et qui sont accessibles via des instructions spécialisées, sont fortement couplées au chemin de données du processeur. Ces instructions spécialisées sont géné- rées et sélectionnées à partir du graphe de l'application. Notre méthode supporte un ordonnancement sous contrainte de ressources ou sous contrainte de temps. Les résultats expérimentaux obtenus sur les benchmarks MediaBench et MiBench montrent une accélération de l'exécution des applications d'un facteur de 2,3 en moyenne

Ordonnancement pour processeurs à parallélisme d'instructions en utilisant des techniques de recherche de motifs

Dans le but de satisfaire les différentes contraintes matérielles, une exploration architecturale peut permettre de définir les paramètres optimaux d'un processeur VLIW (Very Long Instruction Word) pour une application donnée tels que le nombre d'unités fonctionnelles, le nombre de registres, etc. Les paramètres du processeur sont ajustés en fonction du niveau de parallélisme d'instructions de l'application. De la même manière, l'utilisation de jeux d'instructions spécifiques à une application est adaptée à une utilisation au sein des systèmes embarqués qui sont, dans la majeure partie des cas, dédiés à un traitement spécifique. Toutes ces spécialisations permettent d'améliorer efficacement le rapport entre performance, surface et consommation. Ce rapport présente un nouvel outil dont le but est de définir les paramètres optimaux d'un processeur de type VLIW pour une application donnée en termes de dimensionnement, d'organisation et de spécialisation de son jeu d'instructions. Cet outil repose sur la modélisation des problèmes à résoudre en utilisant la programmation par contraintes et exploite la technique de couverture de graphe à l'aide de motifs de calculs. Différentes structures de processeurs pourront alors être comparées en termes de performance et de complexité matérielle

Survey on Instruction Selection: An Extensive and Modern Literature Review

Instruction selection is one of three optimisation problems involved in the code generator backend of a compiler. The instruction selector is responsible of transforming an input program from its target-independent representation into a target-specific form by making best use of the available machine instructions. Hence instruction selection is a crucial part of efficient code generation. Despite on-going research since the late 1960s, the last, comprehensive survey on the field was written more than 30 years ago. As new approaches and techniques have appeared since its publication, this brings forth a need for a new, up-to-date review of the current body of literature. This report addresses that need by performing an extensive review and categorisation of existing research. The report therefore supersedes and extends the previous surveys, and also attempts to identify where future research should be directed.Comment: Major changes: - Merged simulation chapter with macro expansion chapter - Addressed misunderstandings of several approaches - Completely rewrote many parts of the chapters; strengthened the discussion of many approaches - Revised the drawing of all trees and graphs to put the root at the top instead of at the bottom - Added appendix for listing the approaches in a table See doc for more inf

ASAM: Automatic Architecture Synthesis and Application Mapping,

Abstract -This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable applicationspecific instruction-set processors (ASIPs). It presents an overview of the research being currently performed in the scope of the European project ASAM (Architecture Synthesis and Application Mapping) of the ARTEMIS program. The paper briefly presents the results of our analysis of the main problems to be solved and challenges to be faced in the design of such heterogeneous MPSoCs. It explains which system, design, and electronic design automation (EDA) concepts seem to be adequate to resolve the problems and address the challenges. Finally, it introduces and briefly discusses the design-flow and its main stages proposed by the ASAM project consortium to enable an effective and efficient solution of these problems. Index Terms-embedded systems, heterogeneous multiprocessor system-on-chip (MPSoC), customizable ASIPs, architecture synthesis, MPSoC and ASIP design automation

ASAM: Automatic Architecture Synthesis and Application Mapping

This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable application-specific instruction-set processors (ASIPs). It presents an over-view of the research being currently performed in the scope of the European project ASAM of the ARTEMIS program. The paper briefly presents the results of our analysis of the main problems to be solved and challenges to be faced in the design of such heterogeneous MPSoCs. It explains which system, design, and electronic design automation (EDA) concepts seem to be adequate to resolve the problems and address the challenges. Finally, it introduces and briefly discusses the ASAM design-flow and its main stages

8th. International congress on archaeology computer graphica. Cultural heritage and innovation

El lema del Congreso es: 'Documentación 3D avanzada, modelado y reconstrucción de objetos patrimoniales, monumentos y sitios.Invitamos a investigadores, profesores, arqueólogos, arquitectos, ingenieros, historiadores de arte... que se ocupan del patrimonio cultural desde la arqueología, la informática gráfica y la geomática, a compartir conocimientos y experiencias en el campo de la Arqueología Virtual. La participación de investigadores y empresas de prestigio será muy apreciada. Se ha preparado un atractivo e interesante programa para participantes y visitantes.Lerma García, JL. (2016). 8th. International congress on archaeology computer graphica. Cultural heritage and innovation. Editorial Universitat Politècnica de València. http://hdl.handle.net/10251/73708EDITORIA