865 research outputs found
LC-VCO design optimization methodology based on the gm/ID ratio for nanometer CMOS technologies
In this paper, an LC voltage-controlled oscillator (LC-VCO) design optimization methodology based on the gm/ID technique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 μA from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier
Semi-empirical model of MOST and passive devices focused on narrowband RF blocks
This paper presents a semi-empirical modeling of MOST and passive elements to be used in narrowband
radiofrequency blocks for nanometer technologies. This model is based on a small set of look-up
tables (LUTs) obtained via electrical simulations. The MOST description is valid for all-inversion regions
of MOST and the data is extracted as function of the gm=ID characteristic; for the passive devices the
LUTs include a simplified model of the element and its principal parasitic at the working frequency
f0. These semi-empirical models are validated by designing a set of 2.4-GHz LNAs and 2.4-GHz and
5-GHz VCOs in three different MOST inversion regions
Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation
This paper presents a simple but accurate semi-empirical model especially focused on 65 nm MOST (MOS transistor) technologies and radio-frequency (RF) applications. It is obtained by means of simple dc and noise simulations extracted over a constrained set of MOSTs. The fundamental variable of the model is the MOST transconductance to current drain ratio gm/ID. Specifically it comprises the large signal DC normalized current, all conductances and transconductances and the normalized intrinsic capacitances. As well, noise MOST characteristics of flicker noise, white noise and MOST corner frequency description are provided. To validate the referred model the widely utilized cascoded common source low noise amplifier (CS-LNA), in 2.5 GHz and 5.3 GHz RF applications is picked. For the presented set of designs different gm/ID ratios are considered. Finally, the computed results are assessed by comparing with the outcomes of electrical simulations.Ministerio de Economía y Competitividad TEC2011-2830
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm
A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281
Concepts and methods in optimization of integrated LC VCOs
Underlying physical mechanisms controlling the noise properties of oscillators are studied. This treatment shows the importance of inductance selection for oscillator noise optimization. A design strategy centered around an inductance selection scheme is executed using a practical graphical optimization method to optimize phase noise subject to design constraints such as power dissipation, tank amplitude, tuning range, startup condition, and diameters of spiral inductors. The optimization technique is demonstrated through a design example, leading to a 2.4-GHz fully integrated, LC voltage-controlled oscillator (VCO) implemented using 0.35-μm MOS transistors. The measured phase-noise values are -121, -117, and -115 dBc/Hz at 600-kHz offset from 1.91, 2.03, and 2.60-GHz carriers, respectively. The VCO dissipates 4 mA from a 2.5-V supply voltage. The inversion mode MOSCAP tuning is used to achieve 26% of tuning range. Two figures of merit for performance comparison of various oscillators are introduced and used to compare this work to previously reported results
Semi-empirical model of MOST and passive devices focused on narrowband RF blocks
Trabajo presentado al DCIS celebrado en Avignon (Francia) del 28 al 30 de noviembre de 2012.This paper presents a semi-empirical modeling of MOST and passive elements to be used in narrowband radiofrequency blocks for nanometer technologies. This model is based on a small set of look-up tables (LUTs) obtained via electrical simulations. The MOST description is valid for all-inversion regions of MOST and the data is extracted as function of the gm=ID characteristic; for the passive devices the LUTs include a simplified model of the element and its principal parasitic at the working frequency f0. These semi-empirical models are validated by designing a set of 2.4-GHz LNAs and 2.4-GHz and 5-GHz VCOs in three different MOST inversion regions.This work has been financed in part by the Junta de Andalucía project P09-TIC-5386 and the Ministerio de Economia y Competitividad project TEC2011-28302, both of them co-financed by the FEDER program.Peer Reviewe
Low Power Decoding Circuits for Ultra Portable Devices
A wide spread of existing and emerging battery driven wireless devices do not necessarily demand high data rates. Rather, ultra low power, portability and low cost are the most desired characteristics. Examples of such applications are wireless sensor networks (WSN), body area networks (BAN), and a variety of medical implants and health-care aids. Being small, cheap and low power for the individual transceiver nodes, let those to be used in abundance in remote places, where access for maintenance or recharging the battery is limited. In such scenarios, the lifetime of the battery, in most cases, determines the lifetime of the individual nodes. Therefore, energy consumption has to be so low that the nodes remain operational for an extended period of time, even up to a few years. It is known that using error correcting codes (ECC) in a wireless link can potentially help to reduce the transmit power considerably. However, the power consumption of the coding-decoding hardware itself is critical in an ultra low power transceiver node. Power and silicon area overhead of coding-decoding circuitry needs to be kept at a minimum in the total energy and cost budget of the transceiver node. In this thesis, low power approaches in decoding circuits in the framework of the mentioned applications and use cases are investigated. The presented work is based on the 65nm CMOS technology and is structured in four parts as follows: In the first part, goals and objectives, background theory and fundamentals of the presented work is introduced. Also, the ECC block in coordination with its surrounding environment, a low power receiver chain, is presented. Designing and implementing an ultra low power and low cost wireless transceiver node introduces challenges that requires special considerations at various levels of abstraction. Similarly, a competitive solution often occurs after a conclusive design space exploration. The proposed decoder circuits in the following parts are designed to be embedded in the low power receiver chain, that is introduced in the first part. Second part, explores analog decoding method and its capabilities to be embedded in a compact and low power transceiver node. Analog decod- ing method has been theoretically introduced over a decade ago that followed with early proof of concept circuits that promised it to be a feasible low power solution. Still, with the increased popularity of low power sensor networks, it has not been clear how an analog decoding approach performs in terms of power, silicon area, data rate and integrity of calculations in recent technologies and for low data rates. Ultra low power budget, small size requirement and more relaxed demands on data rates suggests a decoding circuit with limited complexity. Therefore, the four-state (7,5) codes are considered for hardware implementation. Simulations to chose the critical design factors are presented. Consequently, to evaluate critical specifications of the decoding circuit, three versions of analog decoding circuit with different transistor dimensions fabricated. The measurements results reveal different trade-off possibilities as well as the potentials and limitations of the analog decoding approach for the target applications. Measurements seem to be crucial, since the available computer-aided design (CAD) tools provide limited assistance and precision, given the amount of calculations and parameters that has to be included in the simulations. The largest analog decoding core (AD1) takes 0.104mm2 on silicon and the other two (AD2 and AD3) take 0.035mm2 and 0.015mm2, respectively. Consequently, coding gain in trade-off with silicon area and throughput is presented. The analog decoders operate with 0.8V supply. The achieved coding gain is 2.3 dB at bit error rates (BER)=0.001 and 10 pico-Joules per bit (pJ/b) energy efficiency is reached at 2 Mbps. Third part of this thesis, proposes an alternative low power digital decoding approach for the same codes. The desired compact and low power goal has been pursued by designing an equivalent digital decoding circuit that is fabricated in 65nm CMOS technology and operates in low voltage (near-threshold) region. The architecture of the design is optimized in system and circuit levels to propose a competitive digital alternative. Similarly, critical specifications of the decoder in terms of power, area, data rate (speed) and integrity are reported according to the measurements. The digital implementation with 0.11mm2 area, consumes minimum energy at 0.32V supply which gives 9 pJ/b energy efficiency at 125 kb/s and 2.9 dB coding gain at BER=0.001. The forth and last part, compares the proposed design alternatives based on the fabricated chips and the results attained from the measurements to conclude the most suitable solution for the considered target applications. Advantages and disadvantages of both approaches are discussed. Possible extensions of this work is introduced as future work
Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS
In questo lavoro si presenta una metodologia di
progettazione elettronica a livello di sistema,
affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su
campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di
equazioni atti a selezionare le configurazione di
interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre,
il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso
An Ultra Low-Power Programmable Voltage Reference for Power-Constrained Electronic Systems
This paper proposes a novel architecture for the generation of a programmable voltage reference: the background-
calibrated (BC)-PVR. Our mixed-signal architecture periodically calibrates a static ultra low-power voltage reference generator, from an accurate bandgap reference. The portion of the chip used for the calibration can be powered down with a programmable duty-cycle. The system aims to fully exploit the small temperature derivative vs time DT of several application domains to minimize the average current consumption. The BC-PVR has been designed and implemented in TSMC 55-nm CMOS technology, and it achieves the largest reported programming reference output
◦range [0.42 - 2.52] V, over the temperature range [-20 , 85] C.
The duty-cycle mode allows nanoampere current consumption, and the large design flexibility permits to optimize the system performance for the specific application. These features make the BC-PVR very well-suited for power-constrained electronic systems
A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier
Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed-loop power control and operates under supply voltages from 2.9 V to 5.5 V in a standard micro-lead-frame package. It shows no oscillations, degradation, or failures for over 2000 hours of operation with a supply of 6 V at 135° under a VSWR of 15:1 at all phase angles and has also been tested for more than 2 million device-hours (with ongoing reliability monitoring) without a single failure under nominal operation conditions. It produces up to +35 dBm of RF power with power-added efficiency of 51%
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