Copper Metal for Semiconductor Interconnects

Resistance-capacitance (RC) delay produced by the interconnects limits the speed of the integrated circuits from 0.25 mm technology node. Copper (Cu) had been used to replace aluminum (Al) as an interconnecting conductor in order to reduce the resistance. In this chapter, the deposition method of Cu films and the interconnect fabrication with Cu metallization are introduced. The resulting integration and reliability challenges are addressed as well

차세대 반도체 배선을 위한 코발트 합금 자가형성 확산방지막 재료 설계 및 전기적 신뢰성에 대한 연구

학위논문(박사) -- 서울대학교대학원 : 공과대학 재료공학부, 2022.2. 주영창.Recently, the resistance-capacitance (RC) delay of the Cu interconnects in metal 1 (M1) level has been increased rapidly due to the reduction of the interconnect linewidth along with the transistor scaling down, and the interconnect reliability becomes a severe issue again. In order to overcome interconnect performance problems and move forward to the next-generation interconnects system, study on low resistivity (ρo) and low electron mean free path (λ) metals was conducted. Generally, metals such as Cobalt (Co), Ruthenium (Ru), and Molybdenum (Mo) are mentioned as candidates for next-generation interconnect materials, and since they have a low ρo × λ value, it is expected that the influence of interface scatterings and surface scattering can be minimized. However, harsh operating environments such as high electric fields, critical Joule heating, and reduction of the pitch size are severely deteriorating the performance of electronic devices as well as device reliability. For example, since time dependent dielectric breakdown (TDDB) problems for next-generation interconnect system have been reported recently, it is necessary to study alternative barrier materials and processes to improve the interconnect reliability. Specifically, extrinsic dielectric breakdown due to penetration of Co metal ions in high electric fields has been reported as a reliability problem to be solved in Co interconnect systems. Therefore, there is a need for new material system design and research on a robust diffusion barrier that prevents metal ions from penetrating into the dielectric, thereby improving the reliability of Co interconnects. Moreover, in order to lower the resistance of the interconnect, it is necessary to develop an ultra-thin barrier. This is because even a barrier with good reliability characteristics will degrade chip performance if it takes up a lot of volume in the interconnect. The recommended thickness for a single diffusion barrier layer is currently reported to be less than 2.5 nm. As a result, it is essential to develop materials that comprehensively consider performance and reliability. In this study, we designed a Co alloy self-forming barrier (SFB) material that can make sure of low resistance and high reliability for Co interconnects, which is attracting attention as a next-generation interconnect system. The self-forming barrier methodology induces diffusion of an alloy dopant at the interface between the metal and the dielectric during the annealing process. And the diffused dopant reacts with the dielectric to form an ultra-thin diffusion barrier. Through this methodology, it is possible to improve reliability by preventing the movement of metal ions. First of all, material design rules were established to screen the appropriate alloy dopants and all CMOS-compatible metals were investigated. Dopant resistivity, intermetallic compound formation, solubility in Co, activity coefficient in Co, and oxidation tendency is considered as the criteria for the dopant to escape from the Co matrix and react at the Co/SiO2 interface. In addition, thermodynamic calculations were performed to predict which phases would be formed after the annealing process. Based on thermodynamic calculations, 5 dopant metals were selected, prioritized for self-forming behavior. And the self-forming material was finally selected through thin film and device analysis. We confirmed that Cr, Zn, and Mn out-diffused to the surface of the thin film structure using X-ray photoelectron spectroscopy (XPS) depth profile and investigated the chemical state of out-diffused dopants through the analysis of a binding energy. Cr shows the most ideal self-forming behavior with the SiO2 dielectric and reacted with oxygen to form a Cr2O3 barrier. In metal-insulator-semiconductor (MIS) structure, out-diffused Cr reacts with SiO2 at the interface and forms a self-formed single layer. It was confirmed that the thickness of the diffusion barrier layer is about 1.2 nm, which is an ultra-thin layer capable of minimizing the total effective resistance. Through voltage-ramping dielectric breakdown (VRDB) tests, Co-Cr alloy showed highest breakdown voltage (VBD) up to 200 % than pure Co. The effect of Cr doping concentration and heat treatment condition applicable to the interconnect process was confirmed. When Cr was doped less than 1 at%, the robust electrical reliability was exhibited. Also, it was found that a Cr2O3 interfacial layer was formed when annealing process was performed at 250 °C or higher for 30 minutes or longer. In other words, Co-Cr alloy is well suited for the interconnect process because current interconnect process temperature is below 400 °C. And when the film thickness was lowered from 150 nm to 20 nm, excellent VBD values were confirmed even at high Cr doping concentration (~7.5 at%). It seems that the amount of Cr present at the Co/SiO2 interface plays a very important role in improving the Cr oxide SFB quality. Physical modeling is necessary to understand the amount of Cr at the interface according to the interconnect volumes and the reliability of the Cr oxide self-forming barrier. TDDB lifetime test also performed and Co-Cr alloy interconnect shows a highly reliable diffusion barrier property of self-formed interfacial layer. The DFT analysis also confirmed that Cr2O3 is a very promising barrier material because it showed a higher energy barrier value than the TiN diffusion barrier currently being studied. A Co-based self-forming barrier was designed through thermodynamic calculations that take performance and reliability into account in interconnect material system. A Co interconnect system with an ultra-thin Cr2O3 diffusion barrier with excellent reliability is proposed. Through this design, it is expected that high-performance interconnects based on robust reliability in the advanced interconnect can be implemented in the near future.최근 반도체 소자 스케일링에 따른 배선 선폭 감소로 M0, M1영역에서의 metal 비저항이 급격히 증가하여 배선에서의 RC delay가 다시 한번 크게 문제가 되고 있다. 이를 해결하기 위해서 차세대 배선 시스템에서는 낮은 비저항과 electron mean free path (EMFP)을 가지는 물질 연구가 진행되었다. 대표적으로 Co, Ru, Mo와 같은 금속들이 차세대 배선 재료 후보로 언급되고 있으며 낮은 ρ0 × λ 값을 갖기 때문에 interface (surface) scattering과 grain boundary scattering 영향을 최소화할 수 있을 것으로 보고 있다. 하지만 가혹한 electrical field와 높은 Joule heating이 발생하는 동작 환경으로 인해 performance뿐만 아니라 소자 신뢰성이 더 열악한 상황에 놓여있다. 예를 들어 차세대 금속에 대한 time dependent dielectric breakdown (TDDB) 신뢰성 문제가 보고되고 있기 때문에 이를 보안할 확산방지막 물질 및 공정연구가 필요하다. 특히 높은 전기장에서 Co ion이 유전체로 침투하여 extrinsic dielectric breakdown 신뢰성 문제가 최근 보고되고 있다. 따라서 금속 이온이 유전체 내부로 침투하는 것을 방지하여, Co 배선의 신뢰성을 향상시킬 수 견고한 확산방지막 개발 및 새로운 배선 시스템 설계가 필요한 시점이다. 또한, 배선 저항을 낮추기 위해서는 매우 얇은 확산방지막 개발이 필요하다. 신뢰성이 좋은 확산방지막이라도 배선에서 많은 영역을 차지할 경우 전체 성능이 저하되기 때문이다. Cu 확산방지막으로 사용되고 있는 TaN 층은 2.5 nm 보다 얇을 경우 신뢰성이 급격히 나빠지므로 2.5 nm보다 얇은 두께의 견고한 확산방지막 개발이 필요하다. 본 연구는 차세대 반도체 배선 물질로 주목받고 있는 Co 금속에 대하여 저저항·고신뢰성을 확보할 수 있는 Co alloy 자가형성 확산방지막 (Co alloy self-forming barrier, SFB) 소재 디자인하였다. 자가형성 확산방지막 방법론은 열처리 과정에서 금속과 유전체 계면에서 도펀트가 확산하게 된다. 그리고 확산되니 도펀트는 얇은 확산방지막을 형성하는 방법론이다. 이 방법론을 통해 금속 이온의 이동을 방지하여 Co 배선 신뢰성을 향상시킬 수 있을 것으로 예상하였다. 우선, Co 합금상에서 적절한 도펀트를 찾기 위해서 CMOS 공정에 적용 가능한 금속들을 선별하였다. 도펀트 저항, 금속간 화합물 형성 여부, Co내 고용도, Co alloy에서의 활성계수, 산화도, Co/SiO2 계면에서의 안정상을 열역학적 계산을 통해서 물질 선정 기준으로 세웠다. 열역학적 계산을 기반으로 9개의 도펀트 금속이 선택되었으며, Co 합금 자가형성 확산방지막 기준에 따라서 우선 순위를 지정하였다. 그리고 최종적으로 박막과 소자 신뢰성 평가를 통해서 가장 적합한 자가형성 확산방지막 물질을 선정하였다. X-ray photoelectron spectroscopy (XPS) 분석을 이용하여 Cr, Zn, Mn이 박막 구조의 표면으로 외부 확산 여부를 확인하고 결합 에너지 분석을 통해 외부로 확산된 도펀트의 화학적 상태를 조사하였다. 분석 결과 Cr, Zn, Mn이 유전체 계면으로 확산되어 산소와 반응하여oxide/silicate 확산 방지막 (e.g. Cr2O3, Zn2SiO4, MnSiO3)을 형성한 것을 확인하였다. 그 중 Cr은 SiO2 유전체와 함께 가장 이상적인 자기 형성 거동을 나타내며 산소와 반응하여 Cr2O3 층을 형성하는 것을 확인하였다. MIS (Metal-Insulator-Semiconductor) 구조에서도 외부로 확산된 Cr은 계면에서 SiO2와 반응하여 Cr2O3 자가형성 확산방지막이 형성되었다. 확산방지층의 두께는 약 1.2nm로 전체 유효저항을 최소화할 수 있는 충분히 얇은 두께를 확보하였다. VRDB (Voltage-Ramping Dielectric Breakdown) 테스트를 통해 Co-Cr 합금은 순수 Co보다 최대 200% 높은 항복 전압 (breakdown voltage)을 보였다. 반도체 배선 공정에 적용할 수 있는 Cr 도핑 농도와 열처리 조건의 영향을 확인하였다. Cr이 1at% 미만으로 도핑되었을 때 우수한 전기적 신뢰성을 나타내었다. 또한, 250℃ 이상에서 30분 이상 열처리를 하였을 때 Cr2O3 계면층이 형성됨을 알 수 있었다. 즉, 현재 배선 공정 온도가 400°C 미만이기 때문에 Co-Cr 합금이 배선 공정에 적용 가능함을 확인하였다. TDDB 수명 테스트도 수행되었으며 Co-Cr 합금 배선은 자체 형성된 계면층의 매우 안정적인 확산 장벽 특성을 보여주었다. DFT 분석은 Cr2O3자가형성 확산방지막이 현재 연구되고 있는 TiN 확산 장벽보다 더 높은 에너지 장벽 값을 보여주기 때문에 매우 유망한 확산방지막임을 보여주었다. 본 연구는 반도채 배선 물질 시스템에서 성능과 신뢰성을 고려한 열역학적 계산을 통해 Co 기반 자가형성 확산방지막을 설계하였다. 실험 결과 신뢰성이 우수하고 아주 얇은 Cr2O3 확산방지막이 있는 Co-Cr 합금이 제안하였다. 물질 설계와 전기적 신뢰성 검증을 Co/Cr2O3/SiO2 물질 시스템을 제안하였고 앞으로의 다가올 차세대 배선에서 구현될 수 있을 것으로 기대된다.Abstract i Table of Contents v List of Tables ix List of Figures xii Chapter 1. Introduction 1 1.1. Scaling down of VLSI systems 1 1.2. Driving force of interconnect system evolution 7 1.3. Driving force of beyond Cu interconnects 11 1.4. Objective of the thesis 18 1.5. Organization of the thesis 21 Chapter 2. Theoretical Background 22 2.1. Evolution of interconnect systems 22 2.1.1. Cu/barrier/low-k interconnect system 22 2.1.2. Process developments for interconnect reliability 27 2.1.3. 3rd generation of interconnect system 31 2.2 Thermodynamic tools for Co self-forming barrier 42 2.2.1 Binary phase diagram 42 2.2.2 Ellingham diagram 42 2.2.3 Activity coefficient 43 2.3. Reliability of Interconnects 45 2.3.1. Current conduction mechanisms in dielectrics 45 2.3.2. Reliability test vehicles 50 2.3.3. Dielectric breakdown assessment 52 2.3.4. Dielectric breakdown mechanisms 55 2.3.5. Reliability test: VRDB and TDDB 56 2.3.6. Lifetime models 57 Chapter 3. Experimental Procedures 60 3.1. Thin film deposition 60 3.1.1. Substrate preparation 60 3.1.2. Oxidation 61 3.1.3. Co alloy deposition using DC magnetron sputtering 61 3.1.4. Annealing process 65 3.2. Thin film characterization 67 3.2.1. Sheet resistance 67 3.2.2. X-ray photoelectron spectroscopy (XPS) 68 3.3. Metal-Insulator-Semiconductor (MIS) device fabrication 70 3.3.1. Patterning using lift-off process 70 3.3.2. TDDB packaging 72 3.4. Reliability analysis 74 3.4.1. Electrical reliability analysis 74 3.4.2. Transmission electron microscopy (TEM) analysis 75 3.5. Computation 76 3.5.1 FactsageTM calculation 76 3.5.2. Density Functional Theory (DFT) calculation 77 Chapter 4. Co Alloy Design for Advanced Interconnects 78 4.1. Material design of Co alloy self-forming barrier 78 4.1.1. Rule of thumb of Co-X alloy 78 4.1.2. Co alloy phase 80 4.1.3. Out-diffusion stage 81 4.1.4. Reaction step with SiO2 dielectric 89 4.1.5. Comparison criteria 94 4.2. Comparison of Co alloy candidates 97 4.2.1. Thin film resistivity evaluation 97 4.2.2. Self-forming behavior using XPS depth profile analysis 102 4.2.3. MIS device reliability test 110 4.3 Summary 115 Chapter 5. Co-Cr Alloy Interconnect with Robust Self-Forming Barrier 117 5.1. Compatibility of Co-Cr alloy SFB process 117 5.1.1. Effect of Cr doping concentration 117 5.1.2. Annealing process condition optimization 119 5.2. Reliability of Co-Cr interconnects 122 5.2.1. VRDB quality test with Co-Cr alloys 122 5.2.2. Lifetime evaluation using TDDB method 141 5.2.3. Barrier mechanism using DFT 142 5.3. Summary 145 Chapter 6. Conclusion 148 6.1. Summary of results 148 6.2. Research perspectives 150 References 151 Abstract (In Korean) 166 Curriculum Vitae 169박

Estudo da eletromigração em circuitos integrados na fase de projeto

Orientadores: Roberto Lacerda de Orio, Leandro Tiago ManeraTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: O dano por eletromigração nas interconexões é um gargalo bem conhecido dos circuitos integrados, pois causam problemas de confiabilidade. A operação em temperaturas e densidades de corrente elevadas acelera os danos, aumentando a resistência da interconexão e, portanto, reduzindo a vida útil do circuito. Este problema tem se acentuado com o escalonamento da tecnologia. Para garantir a confiabilidade da interconexão e, como consequência, a confiabilidade do circuito integrado, métodos tradicionais baseados no chamado Efeito Blech e numa densidade de corrente máxima permitida são implementados durante o projeto da interconexão. Esses métodos, no entanto, não levam em consideração o impacto da eletromigração no desempenho do circuito. Neste trabalho, a abordagem tradicional é estendida e um método para avaliar o efeito da eletromigração no desempenho de circuito integrado é desenvolvido. O método é implementado em uma ferramenta que identifica as interconexões críticas em um circuito integrado e sugere larguras adequadas com base em diferentes critérios para mitigar os danos à eletromigração e aumentar a confiabilidade. Além disso, é determinada a variação dos parâmetros de desempenho do circuito conforme a resistência das interconexões aumenta. A ferramenta é incorporada ao fluxo de projeto do circuito integrado e usa os dados dos kits de projeto e relatórios diretamente disponíveis no ambiente de projeto. Uma análise precisa da distribuição de temperatura na estrutura de interconexão é essencial para uma melhor avaliação da confiabilidade da interconexão. Portanto, é implementado um modelo para calcular a temperatura em cada nível de metalização da estrutura de interconexão. A distribuição de temperatura nas camadas de metalização de diferentes tecnologias é investigada. É mostrado que a temperatura no Metal 1 da tecnologia Intel 10 nm aumenta 75 K, 12 K mais alta que no Metal 2. Como esperado, as camadas mais próximas dos transistores sofrem um aumento de temperatura mais significativo. A ferramenta é aplicada para avaliar eletromigração nas interconexões e na robustez de diferentes circuitos, como um oscilador em anel, um circuito gerador de tensão de referência tipo bandgap e um amplificador operacional. O amplificador operacional, em particular, é cuidadosamente estudado. A metodologia proposta identifica interconexões críticas que quando danificadas por eletromigração causam grandes variações no desempenho do circuito. No pior cenário, a frequência de corte do circuito varia 65% em 5 anos de operação. Uma descoberta interessante é que a metodologia proposta identifica interconexões críticas que não seriam identificadas pelos critérios tradicionais. Essas interconexões operam com densidades de corrente abaixo do limite recomendado pelas regras de projeto. No entanto, uma dessas interconexões leva a uma variação de 30% no ganho do amplificador operacional. Em resumo, a ferramenta proposta verificou que dos 20% de caminhos com uma densidade crítica de corrente, apenas 3% degradam significativamente o desempenho do circuito. Este trabalho traz o estudo da confiabilidade das interconexões e de circuitos integrados para a fase de projeto, o que permite avaliar a degradação do desempenho do circuito antecipadamente durante o seu desenvolvimento. A ferramenta desenvolvida permite ao projetista identificar interconexões críticas que não seriam detectadas usando o critério de densidade máxima de corrente, levando a uma análise mais ampla e precisa da robustez de circuitos integradosAbstract: Electromigration damage in interconnects is a well-known bottleneck of integrated circuits, because it causes reliability problems. Operation at high temperatures and current densities accelerates the damage, increasing the interconnect resistance and, therefore, reducing the circuit lifetime. This issue has been accentuated with the technology downscaling. To guarantee the interconnect reliability and, as a consequence, the integrated circuit reliability, traditional methods based on the so-called Blech Effect and on the maximum allowed current density are implemented during interconnect design. These methods, however, do not take into account the impact of the electromigration on the circuit performance. In this work the traditional approach is extended and a method to evaluate the effect of the electromigration in an integrated circuit performance is developed. The method is implemented in a tool which identifies the critical interconnect lines of an integrated circuit and suggests the proper interconnect width based on different criteria to mitigate the electromigration damage and to increase the reliability. In addition, the variation of performance parameters of the circuit as an interconnect resistance changes is determined. The tool is incorporated into the design flow of the integrated circuit and uses the data from design kits and reports directly available from the design environment. An accurate analysis of the temperature distribution on the interconnect structure is essential to a better assessment of the interconnect reliability. Therefore, a model to compute the temperature on each metallization level of the interconnect structure is implemented. The temperature distribution on the metallization layers of different technologies is investigated. It is shown that the temperature in the Metal 1 of the Intel 10 nm can increase by 75 K, 12 K higher than in the Metal 2. As expected, the layers that are closer to the transistors undergo a more significant temperature increase. The tool is applied to evaluate the interconnects and the robustness of different circuits, namely a ring oscillator, a bandgap voltage reference circuit, and an operational amplifier, against electromigration. The operational amplifier, in particular, is thoroughly studied. The proposed methodology identifies critical interconnects which under electromigration cause large variations in the performance of the circuit. In a worst-case scenario, the cutoff frequency of the circuit varies by 65% in 5 years of operation. An interesting finding is that the proposed methodology identifies critical interconnects which would not be identified by the traditional criteria. These interconnects have current densities below the limit recommended by the design rules. Nevertheless, one of such an interconnect leads to a variation of 30% in the gain of the operational amplifier. In summary, the proposed tool verified that from the 20% paths with a critical current density, only 3% degrades significantly the circuit performance. This work brings the study of the reliability of the interconnects and of integrated circuits to the design phase, which provides the assessment of a circuit performance degradation at an early stage of development. The developed tool allows the designer to identify critical interconnects which would not be detected using the maximum current density criterion, leading to more accurate analysis of the robustness of integrated circuitsDoutoradoEletrônica, Microeletrônica e OptoeletrônicaDoutor em Engenharia Elétrica88882.329437/2019-01CAPE

TOWARDS INTEGRATION OF GRAPHENE IN ADVANCED CMOS INTERCONNECT TECHNOLOGY

The integration of graphene into existing state-of-the-art semiconductor manufacturing is a topic of worldwide interest. With its unprecedented electrical, thermal and mechanical properties, graphene is ideally suited for back-end of line (BEOL) technology to boost the performance of on-chip copper (Cu) interconnects. However, the lack of BEOL compatible methods has stymied the true evaluation of Cu/graphene hybrid (Cu-G) technology. The objectives of this thesis proposal are to demonstrate BEOL-compatible graphene growth techniques, and explore various avenues for practical integration of graphene in order to achieve better electrical, thermal and reliability metrics than traditional interconnect technology

DESIGN, MODELING, OPTIMIZATION, AND BENCHMARKING OF INTERCONNECTS AND SCALING TECHNOLOGIES AND THEIR CIRCUIT AND SYSTEM LEVEL IMPACT

This research focuses on the future of integrated circuit (IC) scaling technologies at the device and back end of line (BEOL) level. This work includes high level modeling of different technologies and quantifying potential performance gains on a circuit and system level. From the device side, this research looks at the scaling challenges and the future scaling drivers for conventional charge-based devices implemented at the 7nm technology node and beyond. It examines the system-level performance of stacking device logic in addition to tunneling field effect transistors (TFET) and their potential as beyond-CMOS devices. Finally, this research models and benchmarks BEOL scaling challenges and evaluates proposed technological advancements such as metal barrier scaling for copper interconnects and replacing local interconnects with ruthenium. Potential impact on performance, power, and area of these interconnect technologies is quantified for fully placed and routed circuits.Ph.D

Electromigration modeling and layout optimization for advanced VLSI

textElectromigration (EM) is a critical problem for interconnect reliability in advanced VLSI design. Because EM is a strong function of current density, a smaller cross-sectional area of interconnects can degrade the EM-related lifetime of IC, which is expected to become more severe in future technology nodes. Moreover, as EM is governed by various factors such as temperature, material property, geometrical shape, and mechanical stress, different interconnect structures can have distinct EM issues and solutions to mitigate them. For example, one of the most prominent technologies, die stacking technology of three-dimensional (3D) ICs, can have different EM problems from that of planer ICs, due to their unique interconnects such as through-silicon vias (TSVs). This dissertation investigates EM in various interconnect structures, and applies the EM models to optimize IC layout. First, modeling of EM is developed for chip-level interconnects, such as wires, local vias, TSVs, and multi-scale vias (MSVs). Based on the models, fast and accurate EM-prediction methods are proposed for the chip-level designs. After that, by utilizing the EM-prediction methods, the layout optimization methods are suggested, such as EM-aware routing for 3D ICs and EM-aware redundant via insertion for the future technology nodes in VLSI. Experimental results show that the proposed EM modeling approaches enable fast and accurate EM evaluation for chip design, and the EM-aware layout optimization methods improve EM-robustness of advanced VLSI designs.Electrical and Computer Engineerin

Study of initial void formation and electron wind force for scaling effects on electromigration in Cu interconnects

textThe continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes.Physic

Carbon Nanotube Interconnects for End-of-Roadmap Semiconductor Technology Nodes

Advances in semiconductor technology due to aggressive downward scaling of on-chip feature sizes have led to rapid rises in resistivity and current density of interconnect conductors. As a result, current interconnect materials, Cu and W, are subject to performance and reliability constraints approaching or exceeding their physical limits. Therefore, alternative materials such as nanocarbons, metal silicides, and Ag nanowires are actively considered as potential replacements to meet such constraints. Among nanocarbons, carbon nanotube (CNT) is among the leading replacement candidate for on-chip interconnect vias due to its high aspect-ratio nanostructure and superior currentcarrying capacity to those of Cu, W, and other potential candidates. However, contact resistance of CNT with metal is a major bottleneck in device functionalization. To meet the challenge posed by contact resistance, several techniques are designed and implemented. First, the via fabrication and CNT growth processes are developed to increase the CNT packing density inside via and to ensure no CNT growth on via sidewalls. CNT vias with cross-sections down to 40 nm 40 nm are fabricated, which have linewidths similar to those used for on-chip interconnects in current integrated circuit manufacturing technology nodes. Then the via top contact is metallized to increase the total CNT area interfacing with the contact metal and to improve the contact quality and reproducibility. Current-voltage characteristics of individual fabricated CNT vias are measured using a nanoprober and contact resistance is extracted with a first-reported contact resistance extraction scheme for 40 nm linewidth. Based on results for 40 nm and 60 nm top-contact metallized CNT vias, we demonstrate that not only are their current-carrying capacities two orders of magnitude higher than their Cu and W counterparts, they are enhanced by reduced via resistance due to contact engineering. While the current-carrying capacities well exceed those projected for end-of-roadmap technology nodes, the via resistances remain a challenge to replace Cu and W, though our results suggest that further innovations in contact engineering could begin to overcome such challenge

Investigation of Mn and Ti based self-forming barriers for future back-end-of-the-line interconnects

This thesis focusses on the investigation of the suitability of Mn and Ti-based self-forming barriers for the future generation of interconnects on both thermally grown SiO2 and low-k dielectrics. the self-forming barriers chemically interact with the insulating substrates forming diffusion barriers upon annealing and this fabrication approach has potential application in future generations of interconnect technologies as the resultant barriers can be significantly thinner than the conventionally deposited barrier layers. the principal in-situ characterisation techniques used to study the interface chemistry resulting from the interaction of deposited films with the insulating substrates were soft and hard X-ray photoelectron spectroscopy (XPS and HAXPES). secondary ion mass spectroscopy (SIMS) measurements provided information on the structure of the barriers which could be correlated with the XPS results while electrical measurements (four-point probe and CV measurements) helps in studying the feasibility of the self-forming barriers. Comparison of Mn-based diffusion barriers with and without the incorporation of nitrogen in the film showed that the introduction of nitrogen improved the adhesion of the copper to the dielectric while chemically both had similar interfaces. Cu based alloy films of Mn and Ti were prepared and analysed show that both alloying elements improve the adhesion and electrical characteristics compared to pure copper films. However, while Mn forms a dielectric barrier of manganese silicate, ultrathin films of Ti on SiO2 based dielectrics showed the preferential formation of titanium silicide. Thick cobalt/titanium alloy films were also investigated as a potential interconnect and showed the possibility of using a cobalt-based alloy as a replacement for copper and barrier stack for the future generation of interconnects