Factoring out ordered sections to expose thread-level parallelism

With the rise of multi-core processors, researchers are taking a new look at extending the applicability auto-parallelization techniques. In this paper, we identify a dependence pattern on which autoparallelization currently fails. This dependence pattern occurs for ordered sections, i.e. code fragments in a loop that must be executed atomically and in original program order. We discuss why these ordered sections prohibit current auto-parallelizers from working and we present a technique to deal with them. We experimentally demonstrate the efficacy of the technique, yielding significant overall program speedups

Visual Representation of Text in Web Documents and Its Interpretation

This paper examines the uses of text and its representation on Web documents in terms of the challenges in its interpretation. Particular attention is paid to the significant problem of non-uniform representation of text. This non-uniformity is mainly due to the presence of semantically important text in image form as opposed to the standard encoded text. The issues surrounding text representation in Web documents are discussed in the context of colour perception and spatial representation. The characteristics of the representation of text in image form are examined and research towards interpreting these images of text is briefly described

Visual Representation of Text in Web Documents and Its Interpretation

This paper examines the uses of text and its representation on Web documents in terms of the challenges in its interpretation. Particular attention is paid to the significant problem of non-uniform representation of text. This non-uniformity is mainly due to the presence of semantically important text in image form as opposed to the standard encoded text. The issues surrounding text representation in Web documents are discussed in the context of colour perception and spatial representation. The characteristics of the representation of text in image form are examined and research towards interpreting these images of text is briefly described

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Linux kernel compaction through cold code swapping

There is a growing trend to use general-purpose operating systems like Linux in embedded systems. Previous research focused on using compaction and specialization techniques to adapt a general-purpose OS to the memory-constrained environment, presented by most, embedded systems. However, there is still room for improvement: it has been shown that even after application of the aforementioned techniques more than 50% of the kernel code remains unexecuted under normal system operation. We introduce a new technique that reduces the Linux kernel code memory footprint, through on-demand code loading of infrequently executed code, for systems that support virtual memory. In this paper, we describe our general approach, and we study code placement algorithms to minimize the performance impact of the code loading. A code, size reduction of 68% is achieved, with a 2.2% execution speedup of the system-mode execution time, for a case study based on the MediaBench II benchmark suite

Durability and Smart Condition Assessment of Ultra-High Performance Concrete in Cold Climates

The goals of this study were to develop ecological ultra-high performance concrete (UHPC) with local materials and supplementary cementitious materials and to evaluate the long-term performance of UHPC in cold climates using effective mechanical test methods, such as “smart aggregate” technology and microstructure imaging analysis. The optimal UHPC mixture approximately exhibited compressive strength of 15 ksi, elastic modulus of 5,000 ksi, direct tensile strength of 1.27 ksi, and shrinkage of 630 at 28 days, which are characteristics comparable to those of commercial products and other studies. The tensile strength and modulus of elasticity in tension, dynamic modulus, and wave modulus show slight increases from the original values after 300 freeze-thaw (F-T) cycles, indicating that UHPC has excellent frost resistance in cold climates. Although porosity deterioration was observed in the F-T cyclic conditioning process, no internal damage (cracks or fractures) was found during imaging analysis up to 300 cycles. Since structures for which UHPC would be used are expected to have a longer service life, more F-T cycles are recommended to condition UHPC and investigate its mechanical performance over time. Moreover, continuum damage mechanic-based models have the potential to evaluate damage accumulation in UHPC and its failure mechanism under frost attack and to predict long-term material deterioration and service life