Multi-COBS: A Novel Algorithm for Byte Stuffing at High Throughput

Framing methods are used to break a data stream into packets in most digital communications. The use of a reserved symbol to denote the frame boundaries is a popular practice. This end-of-frame (EOF) marker should be removed from the packet content in a reversible manner. Many strategies, such as the bit and byte stuffing processes employed by high-level data link control (HDLC) and Point-to-Point Protocol (PPP), or the Consistent Overhead Byte Stuffing (COBS), have been devised to perform this goal. These bit and byte stuffing algorithms remove the reserved EOF marker from the packet payload and replace it with some extra information that can be used to undo the action later. The amount of data added is called overhead and is a figure-of-merit of such algorithms, together with the encoding and decoding speed. Multi-COBS, a new byte stuffing algorithm, is presented in this paper. Multi-COBS provides concurrent encoding and decoding, resulting in a performance improvement of factor four or eight in common word-based digital architectures while delivering an average and worst-case overhead equivalent to the state-of-the-art. On the reference 28-nanometer field programmable gate array (FPGA) (Artix-7), Multi-COBS achieves a throughput of 6.6 Gbps, instead of 1.7 Gbps of COBS. Thanks to its parallel elaboration capability, Multi-COBS is ideal for digital systems built in programmable logic as well as modern computers

Bluetooth software on Linux, wireless hand-held devices

In order to enable existing computers (non-Bluetooth ready) to connect to a Bluetooth piconet, a Bluetooth hardware device comprising of the Radio antenna, the baseband and control circuit is used. The digital portion of this device is also known as a Host Controller, HC. In the traditional communication lingo, the Bluetooth Hardware functions, as the Data Communication Equipment (DCE) while the Host is the Data terminal Equipment (DTE). This report discusses the theory and implementation of the communication protocol between the Host and the Host Controller, enabling communication between the computer and the Bluetooth hardwar

AIRNET: A real-time comunications network for aircraft

A real-time local area network was developed for use on aircraft and space vehicles. It uses token ring technology to provide high throughput, low latency, and high reliability. The system was implemented on PCs and PC/ATs operating on PCbus, and on Intel 8086/186/286/386s operating on Multibus. A standard IEEE 802.2 logical link control interface was provided to (optional) upper layer software; this permits the controls designer to utilize standard communications protocols (e.g., ISO, TCP/IP) if time permits, or to utilize a very fast link level protocol directly if speed is critical. Both unacknowledged datagram and reliable virtual circuit services are supported. A station operating an 8 MHz Intel 286 as a host can generate a sustained load of 1.8 megabits per second per station, and a 100-byte message can be delivered from the transmitter's user memory to the receiver's user memory, including all operating system and network overhead, in under 4 milliseconds

FDMA Point-to-Multi-Point Fibre Access System for Latency Sensitive Applications

We present a demo for a multiple uplink access system with real-time services. Several terminals transmit and are detected simultaneously through FDMA. The system can allow latency-sensitive and best-effort applications to share the network

The Design and modeling of input and output modules for an ATM network switch

The purpose of this thesis is to design, model, and simulate both an input and an output module for an ATM network switch. These devices are used to interface an ATM switch with the physical protocol that is transporting data along the actual transmission medium. The I/O modules have been designed specifically to interface with the Synchronous Optical Network (SONET) protocol. This thesis studies the ATM protocol and examines the issues involved with designing an ATM I/O module chipset. A model of the design was then implemented in both C++ and \TTDL. These models were simulated in order to verify functionality and document performance. The intent of this work is to provide the background and models necessary to aid in the further study and development of entire ATM switch architectures. The input and output modules .ire onlv two functional pieces of a complete ATM switch. The software models that have been implemented by this thesis can be integrated with the other necessary functional blocks to form a complete model of a working ATM switch. These functional blocks can then be rearranged and altered to assist in the study of how different switch architectures can effect overall network performance and efficiency. The input and output modules have been designed to be as flexible as possible in order to easily adapt to future modifications

High throughput image compression and decompression on GPUs

Diese Arbeit befasst sich mit der Entwicklung eines GPU-freundlichen, intra-only, Wavelet-basierten Videokompressionsverfahrens mit hohem Durchsatz, das für visuell verlustfreie Anwendungen optimiert ist. Ausgehend von der Beobachtung, dass der JPEG 2000 Entropie-Kodierer ein Flaschenhals ist, werden verschiedene algorithmische Änderungen vorgeschlagen und bewertet. Zunächst wird der JPEG 2000 Selective Arithmetic Coding Mode auf der GPU realisiert, wobei sich die Erhöhung des Durchsatzes hierdurch als begrenzt zeigt. Stattdessen werden zwei nicht standard-kompatible Änderungen vorgeschlagen, die (1) jede Bitebebene in nur einem einzelnen Pass verarbeiten (Single-Pass-Modus) und (2) einen echten Rohcodierungsmodus einführen, der sample-weise parallelisierbar ist und keine aufwendige Kontextmodellierung erfordert. Als nächstes wird ein alternativer Entropiekodierer aus der Literatur, der Bitplane Coder with Parallel Coefficient Processing (BPC-PaCo), evaluiert. Er gibt Signaladaptivität zu Gunsten von höherer Parallelität auf und daher wird hier untersucht und gezeigt, dass ein aus verschiedensten Testsequenzen gemitteltes statisches Wahrscheinlichkeitsmodell eine kompetitive Kompressionseffizienz erreicht. Es wird zudem eine Kombination von BPC-PaCo mit dem Single-Pass-Modus vorgeschlagen, der den Speedup gegenüber dem JPEG 2000 Entropiekodierer von 2,15x (BPC-PaCo mit zwei Pässen) auf 2,6x (BPC-PaCo mit Single-Pass-Modus) erhöht auf Kosten eines um 0,3 dB auf 1,0 dB erhöhten Spitzen-Signal-Rausch-Verhältnis (PSNR). Weiter wird ein paralleler Algorithmus zur Post-Compression Ratenkontrolle vorgestellt sowie eine parallele Codestream-Erstellung auf der GPU. Es wird weiterhin ein theoretisches Laufzeitmodell formuliert, das es durch Benchmarking von einer GPU ermöglicht die Laufzeit einer Routine auf einer anderen GPU vorherzusagen. Schließlich wird der erste JPEG XS GPU Decoder vorgestellt und evaluiert. JPEG XS wurde als Low Complexity Codec konzipiert und forderte erstmals explizit GPU-Freundlichkeit bereits im Call for Proposals. Ab Bitraten über 1 bpp ist der Decoder etwa 2x schneller im Vergleich zu JPEG 2000 und 1,5x schneller als der schnellste hier vorgestellte Entropiekodierer (BPC-PaCo mit Single-Pass-Modus). Mit einer GeForce GTX 1080 wird ein Decoder Durchsatz von rund 200 fps für eine UHD-4:4:4-Sequenz erreicht.This work investigates possibilities to create a high throughput, GPU-friendly, intra-only, Wavelet-based video compression algorithm optimized for visually lossless applications. Addressing the key observation that JPEG 2000’s entropy coder is a bottleneck and might be overly complex for a high bit rate scenario, various algorithmic alterations are proposed. First, JPEG 2000’s Selective Arithmetic Coding mode is realized on the GPU, but the gains in terms of an increased throughput are shown to be limited. Instead, two independent alterations not compliant to the standard are proposed, that (1) give up the concept of intra-bit plane truncation points and (2) introduce a true raw-coding mode that is fully parallelizable and does not require any context modeling. Next, an alternative block coder from the literature, the Bitplane Coder with Parallel Coefficient Processing (BPC-PaCo), is evaluated. Since it trades signal adaptiveness for increased parallelism, it is shown here how a stationary probability model averaged from a set of test sequences yields competitive compression efficiency. A combination of BPC-PaCo with the single-pass mode is proposed and shown to increase the speedup with respect to the original JPEG 2000 entropy coder from 2.15x (BPC-PaCo with two passes) to 2.6x (proposed BPC-PaCo with single-pass mode) at the marginal cost of increasing the PSNR penalty by 0.3 dB to at most 1 dB. Furthermore, a parallel algorithm is presented that determines the optimal code block bit stream truncation points (given an available bit rate budget) and builds the entire code stream on the GPU, reducing the amount of data that has to be transferred back into host memory to a minimum. A theoretical runtime model is formulated that allows, based on benchmarking results on one GPU, to predict the runtime of a kernel on another GPU. Lastly, the first ever JPEG XS GPU-decoder realization is presented. JPEG XS was designed to be a low complexity codec and for the first time explicitly demanded GPU-friendliness already in the call for proposals. Starting at bit rates above 1 bpp, the decoder is around 2x faster compared to the original JPEG 2000 and 1.5x faster compared to JPEG 2000 with the fastest evaluated entropy coder (BPC-PaCo with single-pass mode). With a GeForce GTX 1080, a decoding throughput of around 200 fps is achieved for a UHD 4:4:4 sequence

Controller Area Network to Modbus network bridge to interface gas detection units with Building Management Systems

Building Management Systems (BMS') are computer systems designed to control systems inside buildings or other facilities. While BMS' are common, there is no one size fits all approach. Controller Area Network (CAN) is a communication protocol sometimes used within BMS'. Modbus is a very common industrial communications protocol. The two protocols are not directly compatible and need to be 'bridged’ to communicate with each other. Gas Detection Australia (GDA) design and manufacture gas detection equipment. They have a current and ongoing need to interface Modbus enabled equipment with CAN enabled equipment in client BMS'. This project is sponsored with the aim of producing a network bridge to translate between the two protocols. The specific Modbus variation implemented is Modbus ASCII master. The design was based around the PIC 18F87K22 microprocessor. This was chosen to remain consistent with other GDA products. The communication interfaces were designed using integrated circuits that closely mimic the software development tools. This was a deliberate choice made to make software development simpler and to make it easier to translate source code to the finished product. A testing method was also created to allow the assessment of bridge performance. Testing demonstrated proof of concept using the development board. Separate testing of RS-485 hardware suggests that the full hardware specification is valid. Stress tests were carried out and determined that the bridge could be expected to be capable of responding to four CAN messages per second. The testing was limited by issues relating to the inconsistent operation of the CAN interface