Hardware thread management modeling for precision timed processors

Studies recently and currently in progress address timing demands for Cyber Physical Systems (CPS) applications. Certain areas of research seek to modify modern computer architecture to meet the needs of CPS applications. Moreover, specific modifications in current computer architecture have produced newer computer architectures and processors, such as precision timed (PRET) processors. This thesis focuses on identifying, modeling, and simulating thread management methods in hardware used by the current open-source PRET soft processor, the MultiFire

Linux embebido en un soft-processor Microblaze

Los sistemas embebidos son sistemas dedicados a una única tarea, es por ello que se los llama "sistemas de propósitos específicos". En la actualidad, los sistemas embebidos han logrado un gran auge gracias a sus diferentes campos de aplicaciones y sus bajos costos comparados con sistemas tradicionales [4, 12]. Es muy común el uso cotidiano de sistemas embebidos, ya sea en electrónica de consumo (lavarropas, heladeras, microondas, relojes, consolas de juegos, control remoto, cámaras de video, fax, CD, DVD, GPS, televisión digital), en sistemas de comunicación (sistemas de telefonía, contestadores, celulares, beepers, PDAs, routers), en automóviles (inyección electrónica, frenos, elevadores de vidrios, control de asientos, instrumentación, seguridad), en la industria (instrumentación, monitoreo, control, robótica, control de tráfico, manejo de códigos de barras, ascensores), en medicina (monitores cardíacos, renales y de apnea, marcapasos, máquina de diálisis), entre otros [7]. Por esto, hoy en día, se ha adoptado un nuevo paradigma de diseño de bajo costo el cual ha mostrado gran eficiencia al ser dedicado a una tarea específica, dado que solo se diseñan e implementan los módulos que se van a utilizar y por tanto se usa el hardware estrictamente necesario. Además puede ser optimizado en cualquier momento ya que en la mayoría de las ocasiones, es implementado sobre dispositivos que pueden ser reprogramados. Es así como los sistemas embebidos son la primera opción en el campo de la ingeniería para la solución de problemas específicos. Si un sistema embebido ofrece grandes ventajas, estas serán mayores si se cuenta con un sistema operativo que le brinde al usuario una mayor facilidad a la hora de trabajar y crear un sistema especializado mucho más robusto. Esto se ha logrado gracias a que se cuenta con el sistema operativo Linux, uno de los más estables y difundidos, que puede ser portado a este tipo de hardware a través de diferentes distribuciones (VxWorks, BlueCat, MontaVista linux, ThreadX, uC/OS-II o uClinux, entre otros) a una arquitectura Microblaze de Xilinx en FPGA [1,3,4].Eje: Arquitectura, Redes y Sistemas OperativosRed de Universidades con Carreras en Informática (RedUNCI

FPGA Operating System for Hard Real Time Applications

In mechatronics, as in many others fields, one of the main aspect is the prototyping. Since the mechatronics covers a lot of complex applications, the availability of a common digital platform to use in all of them is a valid help in the prototyping phase of the project. FPGAs are often used as software acceleration in reconfigurable computers (RC), in which the operating system is a standard off-the-shelf real time operating system such as Linux and VxWorks. The object of the first part of the work is to develop a hardware operating system for mechatronic applications, which means that the FPGA device does not host a soft core processor, able to execute one only operation at a time, but it executes many concurrent hard real time functions allowing the user to develop his own application code taking advantage of the main features of the device: concurrency, flexibility and determinism. The second part of the thesis is related to the project of an electronic module that integrates logic and power devices to drive piezoelectric stack actuators and demonstrate experimentally the results in terms of control of piezoelectric stack tip displacement on atest bench. The electronic module controls up to four piezoelectric stack actuators and guarantees that the correct tip displacement is reached starting from a desired profile. The various opening/closing phases of the actuators are tuned in terms of slew rate, timings and values to reach during all the controlled phase. The control parameters are passed to the control unit by means of a host human machine interface or by an external electronic control unit that acts as a supervisor. This part will illustrate all the passages of the design starting from the constitutive equations of the piezoelectric material up to the final architecture of the control law and implementation passing through: • creation of a FEM model of the piezoelectric stack; • construction of the modal residues model; • FEM model validation; • identification of the electrical equivalent circuit of the piezoelectric stack; • design of the power driver circuit; • design of the control loops; A complete model validation is then performed and experimental results are presente

Realisierungsmethodik von applikationsspezifischen Softcore FPGA-Lösungen: in Abhänigkeit von algorithmischen Anforderungen im Einsatzgebiet eingebetteter Systeme

Die vorliegende Dissertation befasst sich mit Prinzipien, Methodiken, Techniken und Realisierungen zur systematischen Entwicklung von komplexen eingebetteten Systemen unter Verwendung von Softcore Prozessoren. Die adressierte Aufgabendomäne ist vor allem die echtzeitkritische Daten- und Bildverarbeitung. Notwendig sind neue Lösungen aufgrund immer leistungsfähigerer eingebetteter Systeme, mit deren Hilfe Aufgabenfelder bedient werden können, die bisher mit diesen Systemen nicht umsetzbar waren. Aufbauend auf den Darstellungen bereits existierender Modelle und Verfahren, wie z. B. dem V-Modell oder dem Hardware-Software Co-Design, wird eine spezielle Realisierungsmethodik für applikationsspezifische Softcore FPGA-Lösungen in Abhängigkeit von algorithmischen Anforderungen in der Aufgabendomäne erarbeitet. In diesem Zusammenhang wird eine Softcore-Bibliothek mit an diese Domäne angepassten Eigenschaften konzipiert und umgesetzt. Das dabei verwendete modellbasierte Vorgehen ermöglicht durch eine hierarchische Beschreibung und Validierung eine zeit- und kosteneffiziente Entwicklung komplexer Systeme. Für jede Abstraktionsebene werden Modelle vorgestellt, die jeweils auf dieser alle notwendigen Anforderungen zur frühzeitigen Fehlererkennung und Fehlervermeidung sowie eine automatisierte Codegenerierung und Optimierungen sinnvoll umsetzen. Durch gezielte Festlegung einzuhaltender Kriterien und Entwicklungsschritte wird dabei in jeder Komponente der Toolchain eine bestmögliche Kombination von zeit- und kosteneffizienter Entwicklung mit der Sicherstellung der Einhaltung harter Echtzeiteigenschaften sowie einer Maximierung der Wiederverwendbarkeit, erreicht. Dabei spielt die Anpassbarkeit der eingebetteten Systeme mit Hilfe von partieller Rekonfiguration, mit der das dynamische Austauschen von Teilen des Softcores oder sogar ganzer Softcore Prozessoren zur Laufzeit ermöglicht wird, eine wichtige Rolle. Es erfolgen ein praktischer Nachweis der Funktionalität der erarbeiteten Modelle sowie ausführliche Experimente über die zeitlichen Anforderungen bei der partiellen Rekonfiguration von Softcore Prozessoren. Die praktischen Ergebnisse der Arbeit zeigen deutlich die Effizienz der Entwicklung von Lösungen mit der konzipierten und umgesetzten Toolchain sowie die Relevanz und Einsetzbarkeit der partiellen Rekonfiguration in diesem Gebiet.This dissertation focuses on principles, methods, techniques and realizations for the systematic development of complex embedded systems using softcore processors. The addressed domain is primarily real-time-critical data and image processing. New solutions are needed due to the increasing performance of embedded systems, allowing for a range of applications that were previously not solvable with these systems. Building on the concepts of already existing models and methods, e.g. the V-model or hardware-software-co-design, a special realization methodology for application-specific softcore FPGA solutions is developed, in conjunction with algorithmic requirements in the addressed domain. In this context, a softcore library with characteristics tailored to this domain is designed and implemented. Through a hierarchical description and validation, the model-based approach used in this thesis enables the time- and cost-efficient development of complex systems. For each abstraction level, models are presented that provide all necessary requisites for early error detection and prevention, as well as mostly automated code generation and code optimization. By defining relevant criteria and development steps, a parsimonious development with respect to time and cost is achieved in each component of the toolchain. This ensures strict adherence to the hard real-time properties and maximizes the reusability of the modules implemented for a specific project. The adaptability of the embedded systems through using partial reconfiguration plays an important role. Partial reconfiguration enables dynamic replacement of parts of the softcore or even entire softcore processors at runtime. A practical evaluation of the functionality of the developed models as well an extensive array of experiments concerning the time requirements for the partial reconfiguration of softcore processors are presented. The practical results of this thesis clearly demonstrate the efficiency of developing solutions with the designed and realized toolchain, as well as the relevance and applicability of partial reconfiguration in the addressed domain

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

Software Defined Applications in Cellular and Optical Networks

abstract: Small wireless cells have the potential to overcome bottlenecks in wireless access through the sharing of spectrum resources. A novel access backhaul network architecture based on a Smart Gateway (Sm-GW) between the small cell base stations, e.g., LTE eNBs, and the conventional backhaul gateways, e.g., LTE Servicing/Packet Gateways (S/P-GWs) has been introduced to address the bottleneck. The Sm-GW flexibly schedules uplink transmissions for the eNBs. Based on software defined networking (SDN) a management mechanism that allows multiple operator to flexibly inter-operate via multiple Sm-GWs with a multitude of small cells has been proposed. This dissertation also comprehensively survey the studies that examine the SDN paradigm in optical networks. Along with the PHY functional split improvements, the performance of Distributed Converged Cable Access Platform (DCCAP) in the cable architectures especially for the Remote-PHY and Remote-MACPHY nodes has been evaluated. In the PHY functional split, in addition to the re-use of infrastructure with a common FFT module for multiple technologies, a novel cross functional split interaction to cache the repetitive QAM symbols across time at the remote node to reduce the transmission rate requirement of the fronthaul link has been proposed.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201