Fault-Tolerant FPGA-Based Systems

This paper presents a new approach to on-line fault tolerance via reconfiguration for the systems mapped onto field programmable gate arrays (FPGAs). The fault detection, based on self-checking technique, is introduced at application level; therefore our approach can detect the faults of configurable logic blocks (CLBs) and routing interconnections in the FPGAs concurrently with the normal system work. A grid of tiles is projected on the FPGA structure and a certain number of spare CLBs is reserved inside every tile. The number of spare CLBs per tile, which will be used as a backup upon detecting any faulty CLB, is estimated in accordance with the probability of failure. After locating the faulty CLBs, the faulty tile will be reconfigured with avoiding the faulty CLBs. Our proposed approach uses a combination of hardware and software redundancy. We assume that a module external to the FPGA controls automatically the reconfiguration process in addition to the diagnosis process (DIRC); typically this is an embedded microprocessor having some storage for the various tile configurations. We have implemented our approach using Xilinx Virtex FPGA. The DIRC code is written in JBits software tools. In response to a component failure this approach capitalizes on the unique reconfiguration capabilities of FPGAs and replaces the affected tile with a functionally equivalent one that does not rely on the faulty component. Unlike fixed structure fault-tolerance techniques for ASICs and microprocessors, this approach allows a single physical component to provide redundant backup for several types of components

A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture

In this paper, we propose an efficient diagnosis scheme to detect and locate the switching network defects/faults in reconfigurable array architecture. This diagnosis scheme performs the test of switching network based on the scan path and fault intersection test methodology to locate the faults occurring in the switching network. After the diagnosis of switching network, the processing element (PE) test can then be initiated through the good switches and links. Errors in testing that cause a good switch, link or PE to be considered as a bad one is called "killing error". The issue of killing error in testing is addressed and the probability of killing error for our diagnosis technique is analyzed and shown to be extremely low. The significance of this approach is the ability to detect and locate the multiple faults in switches, links, and PEs with low testing circuit overhead, and to offer the good test quality in linear diagnosis time.Facultad de Informátic

Automated Debugging Methodology for FPGA-based Systems

Electronic devices make up a vital part of our lives. These are seen from mobiles, laptops, computers, home automation, etc. to name a few. The modern designs constitute billions of transistors. However, with this evolution, ensuring that the devices fulfill the designer’s expectation under variable conditions has also become a great challenge. This requires a lot of design time and effort. Whenever an error is encountered, the process is re-started. Hence, it is desired to minimize the number of spins required to achieve an error-free product, as each spin results in loss of time and effort. Software-based simulation systems present the main technique to ensure the verification of the design before fabrication. However, few design errors (bugs) are likely to escape the simulation process. Such bugs subsequently appear during the post-silicon phase. Finding such bugs is time-consuming due to inherent invisibility of the hardware. Instead of software simulation of the design in the pre-silicon phase, post-silicon techniques permit the designers to verify the functionality through the physical implementations of the design. The main benefit of the methodology is that the implemented design in the post-silicon phase runs many order-of-magnitude faster than its counterpart in pre-silicon. This allows the designers to validate their design more exhaustively. This thesis presents five main contributions to enable a fast and automated debugging solution for reconfigurable hardware. During the research work, we used an obstacle avoidance system for robotic vehicles as a use case to illustrate how to apply the proposed debugging solution in practical environments. The first contribution presents a debugging system capable of providing a lossless trace of debugging data which permits a cycle-accurate replay. This methodology ensures capturing permanent as well as intermittent errors in the implemented design. The contribution also describes a solution to enhance hardware observability. It is proposed to utilize processor-configurable concentration networks, employ debug data compression to transmit the data more efficiently, and partially reconfiguring the debugging system at run-time to save the time required for design re-compilation as well as preserve the timing closure. The second contribution presents a solution for communication-centric designs. Furthermore, solutions for designs with multi-clock domains are also discussed. The third contribution presents a priority-based signal selection methodology to identify the signals which can be more helpful during the debugging process. A connectivity generation tool is also presented which can map the identified signals to the debugging system. The fourth contribution presents an automated error detection solution which can help in capturing the permanent as well as intermittent errors without continuous monitoring of debugging data. The proposed solution works for designs even in the absence of golden reference. The fifth contribution proposes to use artificial intelligence for post-silicon debugging. We presented a novel idea of using a recurrent neural network for debugging when a golden reference is present for training the network. Furthermore, the idea was also extended to designs where golden reference is not present

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)

ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability

Architectural Techniques to Enable Reliable and Scalable Memory Systems

High capacity and scalable memory systems play a vital role in enabling our desktops, smartphones, and pervasive technologies like Internet of Things (IoT). Unfortunately, memory systems are becoming increasingly prone to faults. This is because we rely on technology scaling to improve memory density, and at small feature sizes, memory cells tend to break easily. Today, memory reliability is seen as the key impediment towards using high-density devices, adopting new technologies, and even building the next Exascale supercomputer. To ensure even a bare-minimum level of reliability, present-day solutions tend to have high performance, power and area overheads. Ideally, we would like memory systems to remain robust, scalable, and implementable while keeping the overheads to a minimum. This dissertation describes how simple cross-layer architectural techniques can provide orders of magnitude higher reliability and enable seamless scalability for memory systems while incurring negligible overheads.Comment: PhD thesis, Georgia Institute of Technology (May 2017

Georisks in the Mediterranean and their mitigation

An international scientific conference organised by the Seismic Monitoring and Research Unit, Department of Geoscience, Faculty of Science, Department of Civil and Structural Engineering and Department of Construction and Property Management, Faculty of the Built Environment, University of Malta.Part of the SIMIT project: Integrated civil protection system for the Italo-Maltese cross-border area. Italia-Malta Programme – Cohesion Policy 2007-2013This conference is one of the activities organised within the SIMIT strategic project (Integrated Cross-Border Italo-Maltese System of Civil Protection), Italia-Malta Operational Programme 2007 – 2013. SIMIT aims to establish a system of collaboration in Civil Protection procedures and data management between Sicilian and Maltese partners, so as to guarantee the safety and protection of the citizens and infrastructure of the cross-border area. It is led by the Department of Civil Protection of the Sicilian region, and has as other partners the Department of Civil Protection of Malta and the Universities of Palermo, Catania and Malta. SIMIT was launched in March 2013, and will come to a close in October 2015. Ever since the initial formulation of the project, it has been recognised that a state of national preparedness and correct strategies in the face of natural hazards cannot be truly effective without a sound scientific knowledge of the hazards and related risks. The University of Malta, together with colleagues from other Universities in the project, has been contributing mostly to the gathering and application of scientific knowledge, both in earthquake hazard as well as in building vulnerability. The issue of seismic hazard in the cross-border region has been identified as deserving foremost importance. South-East Sicily in particular has suffered on more than one occasion the effects of large devastating earthquakes. Malta, although fortunately more removed from the sources of such large earthquakes, has not been completely spared of their damaging effects. The drastic increase in the building density over recent decades has raised the level of awareness and concern of citizens and authorities about our vulnerability. These considerations have spurred scientists from the cross-border region to work together towards a deeper understanding of the underlying causes and nature of seismic and associated hazards, such as landslide and tsunami. The SIMIT project has provided us with the means of improving earthquake surveillance and analysis in the Sicily Channel and further afield in the Mediterranean, as well as with facilities to study the behaviour of our rocks and buildings during earthquake shaking. The role of the civil engineering community in this endeavour cannot be overstated, and this is reflected in the incorporation, from the beginning, of the civil engineering component in the SIMIT project. Constructing safer buildings is now accepted to be the major option towards human loss mitigation during strong earthquakes, and this project has provided us with a welcome opportunity for interaction between the two disciplines. Finally the role of the Civil Protection authorities must occupy a central position, as we recognize the importance of their prevention, coordination and intervention efforts, aided by the input of the scientific community. This conference brings together a diversity of geoscientists and engineers whose collaboration is the only way forward to tackling issues and strategies for risk mitigation. Moreover we welcome the contribution of participants from farther afield than the Central Mediterranean, so that their varied experience may enhance our efforts. We are proud to host the conference in the historic city of Valletta, in the heart of the Mediterranean, which also serves as a constant reminder of the responsibility of all regions to protect and conserve our collective heritage.peer-reviewe

Space station needs, attributes, and architectural options study. Volume 2: Program options, architecture, and technology

Mission scenarios and space station architectures are discussed. Electrical power subsystems (EPS), environmental control and life support, subsystems (ECLSS), and reaction control subsystem (RCS) architectures are addressed. Thermal control subsystems, (TCS), guidance/navigation and control (GN and C), information management systems IMS), communications and tracking (C and T), and propellant transfer and storage systems architectures are discussed

Nascom System Development Plan: System Description, Capabilities and Plans

The NASA Communications (Nascom) System Development Plan (NSDP), reissued annually, describes the organization of Nascom, how it obtains communication services, its current systems, its relationship with other NASA centers and International Partner Agencies, some major spaceflight projects which generate significant operational communication support requirements, and major Nascom projects in various stages of development or implementation