57 research outputs found

    Platform-based design, test and fast verification flow for mixed-signal systems on chip

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    This research is providing methodologies to enhance the design phase from architectural space exploration and system study to verification of the whole mixed-signal system. At the beginning of the work, some innovative digital IPs have been designed to develop efficient signal conditioning for sensor systems on-chip that has been included in commercial products. After this phase, the main focus has been addressed to the creation of a re-usable and versatile test of the device after the tape-out which is close to become one of the major cost factor for ICs companies, strongly linking it to model’s test-benches to avoid re-design phases and multi-environment scenarios, producing a very effective approach to a single, fast and reliable multi-level verification environment. All these works generated different publications in scientific literature. The compound scenario concerning the development of sensor systems is presented in Chapter 1, together with an overview of the related market with a particular focus on the latest MEMS and MOEMS technology devices, and their applications in various segments. Chapter 2 introduces the state of the art for sensor interfaces: the generic sensor interface concept (based on sharing the same electronics among similar applications achieving cost saving at the expense of area and performance loss) versus the Platform Based Design methodology, which overcomes the drawbacks of the classic solution by keeping the generality at the highest design layers and customizing the platform for a target sensor achieving optimized performances. An evolution of Platform Based Design achieved by implementation into silicon of the ISIF (Intelligent Sensor InterFace) platform is therefore presented. ISIF is a highly configurable mixed-signal chip which allows designers to perform an effective design space exploration and to evaluate directly on silicon the system performances avoiding the critical and time consuming analysis required by standard platform based approach. In chapter 3 we describe the design of a smart sensor interface for conditioning next generation MOEMS. The adoption of a new, high performance and high integrated technology allow us to integrate not only a versatile platform but also a powerful ARM processor and various IPs providing the possibility to use the platform not only as a conditioning platform but also as a processing unit for the application. In this chapter a description of the various blocks is given, with a particular emphasis on the IP developed in order to grant the highest grade of flexibility with the minimum area occupation. The architectural space evaluation and the application prototyping with ISIF has enabled an effective, rapid and low risk development of a new high performance platform achieving a flexible sensor system for MEMS and MOEMS monitoring and conditioning. The platform has been design to cover very challenging test-benches, like a laser-based projector device. In this way the platform will not only be able to effectively handle the sensor but also all the system that can be built around it, reducing the needed for further electronics and resulting in an efficient test bench for the algorithm developed to drive the system. The high costs in ASIC development are mainly related to re-design phases because of missing complete top-level tests. Analog and digital parts design flows are separately verified. Starting from these considerations, in the last chapter a complete test environment for complex mixed-signal chips is presented. A semi-automatic VHDL-AMS flow to provide totally matching top-level is described and then, an evolution for fast self-checking test development for both model and real chip verification is proposed. By the introduction of a Python interface, the designer can easily perform interactive tests to cover all the features verification (e.g. calibration and trimming) into the design phase and check them all with the same environment on the real chip after the tape-out. This strategy has been tested on a consumer 3D-gyro for consumer application, in collaboration with SensorDynamics AG

    Enhancing Real-time Embedded Image Processing Robustness on Reconfigurable Devices for Critical Applications

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    Nowadays, image processing is increasingly used in several application fields, such as biomedical, aerospace, or automotive. Within these fields, image processing is used to serve both non-critical and critical tasks. As example, in automotive, cameras are becoming key sensors in increasing car safety, driving assistance and driving comfort. They have been employed for infotainment (non-critical), as well as for some driver assistance tasks (critical), such as Forward Collision Avoidance, Intelligent Speed Control, or Pedestrian Detection. The complexity of these algorithms brings a challenge in real-time image processing systems, requiring high computing capacity, usually not available in processors for embedded systems. Hardware acceleration is therefore crucial, and devices such as Field Programmable Gate Arrays (FPGAs) best fit the growing demand of computational capabilities. These devices can assist embedded processors by significantly speeding-up computationally intensive software algorithms. Moreover, critical applications introduce strict requirements not only from the real-time constraints, but also from the device reliability and algorithm robustness points of view. Technology scaling is highlighting reliability problems related to aging phenomena, and to the increasing sensitivity of digital devices to external radiation events that can cause transient or even permanent faults. These faults can lead to wrong information processed or, in the worst case, to a dangerous system failure. In this context, the reconfigurable nature of FPGA devices can be exploited to increase the system reliability and robustness by leveraging Dynamic Partial Reconfiguration features. The research work presented in this thesis focuses on the development of techniques for implementing efficient and robust real-time embedded image processing hardware accelerators and systems for mission-critical applications. Three main challenges have been faced and will be discussed, along with proposed solutions, throughout the thesis: (i) achieving real-time performances, (ii) enhancing algorithm robustness, and (iii) increasing overall system's dependability. In order to ensure real-time performances, efficient FPGA-based hardware accelerators implementing selected image processing algorithms have been developed. Functionalities offered by the target technology, and algorithm's characteristics have been constantly taken into account while designing such accelerators, in order to efficiently tailor algorithm's operations to available hardware resources. On the other hand, the key idea for increasing image processing algorithms' robustness is to introduce self-adaptivity features at algorithm level, in order to maintain constant, or improve, the quality of results for a wide range of input conditions, that are not always fully predictable at design-time (e.g., noise level variations). This has been accomplished by measuring at run-time some characteristics of the input images, and then tuning the algorithm parameters based on such estimations. Dynamic reconfiguration features of modern reconfigurable FPGA have been extensively exploited in order to integrate run-time adaptivity into the designed hardware accelerators. Tools and methodologies have been also developed in order to increase the overall system dependability during reconfiguration processes, thus providing safe run-time adaptation mechanisms. In addition, taking into account the target technology and the environments in which the developed hardware accelerators and systems may be employed, dependability issues have been analyzed, leading to the development of a platform for quickly assessing the reliability and characterizing the behavior of hardware accelerators implemented on reconfigurable FPGAs when they are affected by such faults

    Digital Pulse Width Modulator Techniques For Dc - Dc Converters

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    Recent research activities focused on improving the steady-state as well as the dynamic behavior of DC-DC converters for proper system performance, by proposing different design methods and control approaches with growing tendency to using digital implementation over analog practices. Because of the rapid advancement in semiconductors and microprocessor industry, digital control grew in popularity among PWM converters and is taking over analog techniques due to availability of fast speed microprocessors, flexibility and immunity to noise and environmental variations. Furthermore, increased interest in Field Programmable Gate Arrays (FPGA) makes it a convenient design platform for digitally controlled converters. The objective of this research is to propose new digital control schemes, aiming to improve the steady-state and transient responses of a high switching frequency FPGA-based digitally controlled DC-DC converters. The target is to achieve enhanced performance in terms of tight regulation with minimum power consumption and high efficiency at steady-state, as well as shorter settling time with optimal over- and undershoots during transients. The main task is to develop new and innovative digital PWM techniques in order to achieve: 1. Tight regulation at steady-state: by proposing high resolution DPWM architecture, based on Digital Clock Management (DCM) resources available on FPGA boards. The proposed architecture Window-Masked Segmented Digital Clock Manager-FPGA based Digital Pulse Width Modulator Technique, is designed to achieve high resolution operating at high switching frequencies with minimum power consumption. 2. Enhanced dynamic response: by applying a shift to the basic saw-tooth DPWM signal, in order to benefit from the best linearity and simplest architecture offered by the conventional counter-comparator DPWM. This proposed control scheme will help the compensator reach the steady-state value faster. Dynamically Shifted Ramp Digital Control Technique for Improved Transient Response in DC-DC Converters, is projected to enhance the transient response by dynamically controlling the ramp signal of the DPWM unit

    KAVUAKA: a low-power application-specific processor architecture for digital hearing aids

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    The power consumption of digital hearing aids is very restricted due to their small physical size and the available hardware resources for signal processing are limited. However, there is a demand for more processing performance to make future hearing aids more useful and smarter. Future hearing aids should be able to detect, localize, and recognize target speakers in complex acoustic environments to further improve the speech intelligibility of the individual hearing aid user. Computationally intensive algorithms are required for this task. To maintain acceptable battery life, the hearing aid processing architecture must be highly optimized for extremely low-power consumption and high processing performance.The integration of application-specific instruction-set processors (ASIPs) into hearing aids enables a wide range of architectural customizations to meet the stringent power consumption and performance requirements. In this thesis, the application-specific hearing aid processor KAVUAKA is presented, which is customized and optimized with state-of-the-art hearing aid algorithms such as speaker localization, noise reduction, beamforming algorithms, and speech recognition. Specialized and application-specific instructions are designed and added to the baseline instruction set architecture (ISA). Among the major contributions are a multiply-accumulate (MAC) unit for real- and complex-valued numbers, architectures for power reduction during register accesses, co-processors and a low-latency audio interface. With the proposed MAC architecture, the KAVUAKA processor requires 16 % less cycles for the computation of a 128-point fast Fourier transform (FFT) compared to related programmable digital signal processors. The power consumption during register file accesses is decreased by 6 %to 17 % with isolation and by-pass techniques. The hardware-induced audio latency is 34 %lower compared to related audio interfaces for frame size of 64 samples.The final hearing aid system-on-chip (SoC) with four KAVUAKA processor cores and ten co-processors is integrated as an application-specific integrated circuit (ASIC) using a 40 nm low-power technology. The die size is 3.6 mm2. Each of the processors and co-processors contains individual customizations and hardware features with a varying datapath width between 24-bit to 64-bit. The core area of the 64-bit processor configuration is 0.134 mm2. The processors are organized in two clusters that share memory, an audio interface, co-processors and serial interfaces. The average power consumption at a clock speed of 10 MHz is 2.4 mW for SoC and 0.6 mW for the 64-bit processor.Case studies with four reference hearing aid algorithms are used to present and evaluate the proposed hardware architectures and optimizations. The program code for each processor and co-processor is generated and optimized with evolutionary algorithms for operation merging,instruction scheduling and register allocation. The KAVUAKA processor architecture is com-pared to related processor architectures in terms of processing performance, average power consumption, and silicon area requirements

    Design of electronic systems for automotive sensor conditioning

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    This thesis deals with the development of sensor systems for automotive, mainly targeting the exploitation of the new generation of Micro Electro-Mechanical Sensors (MEMS), which achieve a dramatic reduction of area and power consumption but at the same time require more complexity in the sensor conditioning interface. Several issues concerning the development of automotive ASICs are presented, together with an overview of automotive electronics market and its main sensor applications. The state of the art for sensor interfaces design (the generic sensor interface concept), consists in sharing the same electronics among similar sensor applications, thus saving cost and time-to-market but also implementing a sub-optimal system with area and power overheads. A Platform Based Design methodology is proposed to overcome the limitations of generic sensor interfaces, by keeping the platform generality at the highest design layers and pursuing the maximum optimization and performances in the platform customization for a specific sensor. A complete design flow is presented (up to the ASIC implementation for gyro sensor conditioning), together with examples regarding IP development for reuse and low power optimization of third party designs. A further evolution of Platform Based Design has been achieved by means of implementation into silicon of the ISIF (Intelligent Sensor InterFace) platform. ISIF is a highly programmable mixed-signal chip which allows a substantial reduction of design space exploration time, as it can implement in a short time a wide class of sensor conditioning architectures. Thus it lets the designers evaluate directly on silicon the impact of different architectural choices, as well as perform feasibility studies, sensor evaluations and accurate estimation of the resulting dedicated ASIC performances. Several case studies regarding fast prototyping possibilities with ISIF are presented: a magneto-resistive position sensor, a biosensor (which produces pA currents in presence of surface chemical reactions) and two capacitive inertial sensors, a gyro and a low-g YZ accelerometer. The accelerometer interface has also been implemented in miniboards of about 3 cm2 (with ISIF and sensor dies bonded together) and a series of automatic trimming and characterization procedures have been developed in order to evaluate sensor and interface behaviour over the automotive temperature range, providing a valuable feedback for the implementation of a dedicated accelerometer interface

    Controller implementation using analog reconfigurable hardware (FPAA)

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    This Thesis has the main target to make a research about FPAA/dpASPs devices and technologies applied to control systems. These devices provide easy way to emulate analog circuits that can be reconfigurable by programming tools from manufactures and in case of dpASPs are able to be dynamically reconfigurable on the fly. It is described different kinds of technologies commercially available and also academic projects from researcher groups. These technologies are very recent and are in ramp up development to achieve a level of flexibility and integration to penetrate more easily the market. As occurs with CPLD/FPGAs, the FPAA/dpASPs technologies have the target to increase the productivity, reducing the development time and make easier future hardware reconfigurations reducing the costs. FPAA/dpAsps still have some limitations comparing with the classic analog circuits due to lower working frequencies and emulation of complex circuits that require more components inside the integrated circuit. However, they have great advantages in sensor signal condition, filter circuits and control systems. This thesis focuses practical implementations of these technologies to control system PID controllers. The result of the experiments confirms the efficacy of FPAA/dpASPs on signal condition and control systems.Esta tese tem como principal objectivo fazer uma pesquisa sobre circuitos integrados e tecnologias das FPAA/dpASPs aplicadas a sistemas de controlo. Estes dispositivos possibilitam a emulação de circuitos analógicos que podem ser reconfiguráveis por ferramentas de programação dos próprios fabricantes e no caso dos dpASPs são capazes de ser dinamicamente reconfiguráveis em tempo real. São descritas diferentes tecnologias disponíveis no mercado e também projectos académicos de grupos de investigação. Estas tecnologias são muito recentes e estão em pleno desenvolvimento para alcançar um nível de flexibilidade e integração para penetrar mais facilmente no mercado. Como já ocorre com as CPLD/FPGAs, os FPAA/dpASPs tem o objectivo de aumentar a produtividade, reduzindo o tempo de desenvolvimento e facilitar reconfigurações futuras de hardware, reduzindo os custos. As FPAA/dpASPs ainda tem algumas limitações comparando com os circuitos analógicos clássicos devido a uma menor largura de banda de frequências de trabalho e à dificuldade de emulação de circuitos complexos que requerem mais componentes dentro do circuito integrado e portanto uma maior escala de integração. No entanto, estes circuitos integrados têm grandes vantagens e podem ser utilizados para aplicações de condicionamento do sinal de sensores, circuitos de filtros e sistemas de controlo. Esta tese concentra-se nas implementações práticas destas tecnologias aos sistemas de controlo usando controladores PID. Os resultados das experiências confirmam a eficácia das FPAA/dpASPs no condicionamento de sinal e sistemas de controlo

    On-Board Electronic Control Systems of Future Automated Heavy Machinery

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    The level of automation and wireless communication has increased in heavy machinery recently. This requires utilizing new devices and communication solutions in heavy machinery applications which involve demanding operating conditions and challenging life-cycle management. Therefore, the applied devices have to be robust and hardware architectures flexible, consisting of generic modules. In research and development projects devices that have various communication interfaces and insufficient mechanical and electrical robustness need to be applied. Although this thesis has its main focus on machines utilized as research platforms, many of the challenges are similar with commercial machines.The applicability of typical solutions for data transfer is discussed. Controller area network with a standardized higher level protocol is proposed to be applied where data signalling rates above 1 Mb/s are not required. The main benefits are the availability of robust, generic devices and well-established software tools for configuration management. Ethernet can be utilized to network equipment with high data rates, typically used for perception. Although deterministic industrial Ethernet protocols would fulfil most requirements, the conventional internet protocol suite is likely to be applied due to device availability.Sometimes sensors and other devices without a suitable communication interface need to be applied. In addition, device-related real-time processing or accurate synchronization of hardware signals may be required. A small circuit board with a microcontroller can be utilized as a generic embedded module for building robust, small and cost-efficient prototype devices that have a controller area network interface. Although various microcontroller boards are commercially available, designing one for heavy machinery applications, in particular, has benefits in robustness, size, interfaces, and flexible software development. The design of such a generic embedded module is presented.The device-specific challenges of building an automated machine are discussed. Unexpected switch-off of embedded computers has to be prevented by the control system to avoid file system errors. Moreover, the control system has to protect the batteries against deep discharge when the engine is not running. With many devices, protective enclosures with heating or cooling are required.The electronic control systems of two automated machines utilized as research platforms are presented and discussed as examples. The hardware architectures of the control systems are presented, following the proposed communication solutions as far as is feasible. Several applications of the generic embedded module within the control systems are described. Several research topics have been covered utilizing the automated machines. In this thesis, a cost-efficient operator-assisting functionality of an excavator is presented and discussed in detail.The results of this thesis give not only research institutes but also machine manufacturers and their subcontractors an opportunity to streamline the prototyping of automated heavy machinery

    Portable Waveform Development for Software Defined Radios

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    This work focuses on the question: "How can we build waveforms that can be moved from one platform to another?\u27\u27 Therefore an approach based on the Model Driven Architecture was evaluated. Furthermore, a proof of concept is given with the port of a TETRA waveform from a USRP platform to an SFF SDR platform

    Dynamically reconfigurable architecture for embedded computer vision systems

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    The objective of this research work is to design, develop and implement a new architecture which integrates on the same chip all the processing levels of a complete Computer Vision system, so that the execution is efficient without compromising the power consumption while keeping a reduced cost. For this purpose, an analysis and classification of different mathematical operations and algorithms commonly used in Computer Vision are carried out, as well as a in-depth review of the image processing capabilities of current-generation hardware devices. This permits to determine the requirements and the key aspects for an efficient architecture. A representative set of algorithms is employed as benchmark to evaluate the proposed architecture, which is implemented on an FPGA-based system-on-chip. Finally, the prototype is compared to other related approaches in order to determine its advantages and weaknesses
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