MOS based nanocapacitor using C-AFM

Nanocapacitors are integral devices of nanoscale MOS based integrated circuits and have not yet been realised. We report in this article our results to date on the realisation of such a nanocapacitor through the use of Atomic Force Microscopy (AFM) anodic oxidation to isolate nano-sized squares of poly-silicon, titanium and aluminium on Si/SiO2. The focus of this work is on the Conductive AFM performed topographical and electrical characterization

OXIDATION OF SILICON - THE VLSI GATE DIELECTRIC

Silicon dominates the semiconductor industry for good reasons. One factor is the stable, easily formed, insulating oxide, which aids high performance and allows practical processing. How well can these virtues survive as new demands are made on integrity, on smallness of feature sizes and other dimensions, and on constraints on processing and manufacturing methods? These demands make it critical to identify, quantify and predict the key controlling growth and defect processes on an atomic scale.The combination of theory and novel experiments (isotope methods, electronic noise, spin resonance, pulsed laser atom probes and other desorption methods, and especially scanning tunnelling or atomic force microscopies) provide tools whose impact on models is just being appreciated. We discuss the current unified model for silicon oxidation, which goes beyond the traditional descriptions of kinetic and ellipsometric data by explicitly addressing the issues raised in isotope experiments. The framework is still the Deal-Grove model, which provides a phenomenology to describe the major regimes of behaviour, and gives a base from which the substantial deviations can be characterized. In this model, growth is limited by diffusion and interfacial reactions operating in series. The deviations from Deal-Grove are most significant for just those first tens of atomic layers of oxide which are critical for the ultra-thin oxide layers now demanded. Several features emerge as important. First is the role of stress and stress relaxation. Second is the nature of the oxide closest to the Si, both its defects and its differences from the amorphous stoichiometric oxide further out, whether in composition, in network topology, or otherwise. Thirdly, we must consider the charge states of both fixed and mobile species. In thin films with very different dielectric constants, image terms can be important; these terms affect interpretation of spectroscopies, the injection of oxidant species and relative defect stabilities. This has added importance now that P-b concentrations have been correlated with interfacial stress. This raises further issues about the perfection of the oxide random network and the incorporation of interstitial species like molecular oxygen.Finally, the roles of contamination, particles, metals, hydrocarbons etc are important, as is interface roughness. These features depend on pre-gate oxide cleaning and define the Si surface that is to be oxidized which may have an influence on the features listed above

Characterisation of silicon carbide CMOS devices for high temperature applications

PhD ThesisIn recent years it has become increasingly apparent that there is a large demand for resilient electronics that can operate within environments that standard silicon electronics cease to function such as high power and high voltage applications, high temperatures, corrosive atmospheres and environments exposed to radiation. This has become even more essential due to increased demands for sustainable energy production and the reduction in carbon emissions worldwide, which has put a large burden on a wide range of industrial sectors who now have a significant demand for electronics to meet these needs including; military, space, aerospace, automotive, energy and nuclear. In extreme environments, where ambient temperatures may well exceed the physical limit of silicon-based technologies, SiC based technology offers a lower cost and a smaller footprint solution for operation in such environments due to its advantageous electrical properties such as a high breakdown electric field, high thermal conductivity and large saturation velocity. High quality material on large area wafers (150 mm) is now commercially available, allowing the fabrication of reliable high temperature, high frequency and high current power electronic devices, improving the already optimised silicon based structures. An important advantage of SiC is that it is the only wide band gap compound semiconductor that can be thermally oxidised to grow insulating, high quality SiO2 layers, which makes it an ideal candidate to replace silicon technologies for metal-oxide-semiconductor applications, which is the main focus of this research. Although the technology has made a number of major steps forward over recent years and the commercial manufacturing process has advanced significantly, there still remains a number of issues that need to be overcome in order to fully realise the potential of the material for electronic applications. This thesis describes the characterisation of 4H-SiC CMOS structures that were designed for high temperature applications and fabricated with varying gate dielectric treatments and process steps. The influence of process techniques on the characteristics of metal-oxide-semiconductor (MOS) devices has been investigated by means of electrical characterisation and the results have been compared to theoretical models. The C-V and I-V characteristics of both MOS capacitor and MOSFET structures with varying gate dielectrics on both n-type and p-type 4H-SiC have been analysed to explore the benefits of the varying process techniques that have been employed in the design of the devices. The results show that the field effect mobility characteristic of 4H-SiC MOSFETs are dominated at low perpendicular electric fields by Coulomb scattering and at high electric fields by low surface roughness mobility, which is due to the rough SiC-SiO2 interface. The findings also show that a thermally grown SiO2 layer at the semiconductor-dielectric interface is a beneficial process step that enhances the interfacial characteristics and increases the channel mobility of the MOSFETs. In addition to this it is also found that this technique provides the most beneficial characteristics on both n-type and p-type 4H-SiC, which suggests that it would be the most suitable treatment for a monolithic CMOS process. The impact of threshold voltage adjust ion implantation on both the MIS capacitor and MOSFET structures is also presented and shows that the increasing doses of nitrogen that are implanted to adjust the threshold voltage act to improve the device performance by acting to modify the charge at the interface or within the gate oxide and therefore increase the field effect mobility of the studied devices.Engineering and Physical Sciences Research Council (EPSRC) and Raytheon U

Anisotropic Dielectric Breakdown Strength of Single Crystal Hexagonal Boron Nitride

Dielectric breakdown has historically been of great interest from the perspectives of fundamental physics and electrical reliability. However, to date, the anisotropy in the dielectric breakdown has not been discussed. Here, we report an anisotropic dielectric breakdown strength (EBD) for h-BN, which is used as an ideal substrate for two-dimensional (2D) material devices. Under a well-controlled relative humidity, EBD values in the directions both normal and parallel to the c axis (EBD+c & EBD//c) were measured to be 3 and 12 MV/cm, respectively. When the crystal structure is changed from sp3 of cubic-BN (c-BN) to sp2 of h-BN, EBD+c for h-BN becomes smaller than that for c-BN, while EBD//c for h-BN drastically increases. Therefore, h-BN can possess a relatively high EBD concentrated only in the direction parallel to the c axis by conceding a weak bonding direction in the highly anisotropic crystal structure. This explains why the EBD//c for h-BN is higher than that for diamond. Moreover, the presented EBD value obtained from the high quality bulk h-BN crystal can be regarded as the standard for qualifying the crystallinity of h-BN layers grown via chemical vapor deposition for future electronic applications

Nanoscale characterisation of dielectrics for advanced materials and electronic devices

PhD ThesisStrained silicon (Si) and silicon-germanium (SiGe) devices have long been recognised for their enhanced mobility and higher on-state current compared with bulk-Si transistors. However, the performance and reliability of dielectrics on strained Si/strained SiGe is usually not same as for bulk-Si. Epitaxial growth of strained Si/SiGe can induce surface roughness. The typical scale of surface roughness is generally higher than bulk-Si and can exceed the device size. Surface roughness has previously been shown to impact the electrical properties of the gate dielectric. Conventional macroscopic characterisation techniques are not capable of studying localised electrical behaviour, and thus prevent an understanding of the influence of large scale surface roughness. However scanning probe microscopy (SPM) techniques are capable of simultaneously imaging material and electrical properties. This thesis focuses on understanding the relationship between substrate induced surface roughness and the electrical performance of the overlying dielectric in high mobility strained Si/SiGe devices. SPM techniques including conductive atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) have been applied to tensile strained Si and compressively strained SiGe materials and devices, suitable for enhancing electron and hole mobility, respectively. Gate leakage current, interface trap density, breakdown behaviour and dielectric thickness uniformity have been studied at the nanoscale. Data obtained by SPM has been compared with macroscopic electrical data from the same devices and found to be in good agreement. For strained Si devices exhibiting the typical crosshatch morphology, the electrical performance and reliability of the dielectric is strongly influenced by the roughness. Troughs and slopes of the crosshatch morphology lead to degraded gate leakage and trapped charge at the interface compared with peaks on the crosshatch undulations. Tensile strained Si material which does not exhibit the crosshatch undulation exhibits improved uniformity in dielectric properties. Quantitative agreement has been found for leakage at a device-level and nanoscale, when accounting for the tip area. The techniques developed can be used to study individual defects or regions on dielectrics whether grown or deposited (including high-κ) and on different substrates including strained Si on insulator (SSOI), strained Ge on insulator (SGOI), strained Ge, silicon carbide (SiC) and graphene. Strained SiGe samples with Ge content varying from 0 to 65% have also been studied. The increase in leakage and trapped charge density with increasing Ge extracted from SPM data is in good agreement with theory and macroscopic data. The techniques appear to be very sensitive, with SCM analysis detecting other dielectric related defects on a 20% Ge sample and the effects of the 65% Ge later exceeding the critical thickness (increased defects and variability in characteristics). Further applications and work to advance the use of electrical SPM techniques are also discussed. These include anti-reflective coatings, synthetic chrysotile nanotubes and sensitivity studies.Overseas Research Students Awards Scheme (ORSAS), School International Research Scholarship (SIRS), Newcastle University International Postgraduate Scholarship (NUIPS) and the Strained Si/SiGe platform grant

Molecular Beam Deposition (MBD) and Characterisation of High-k Material as Alternative Gate Oxides for MOS-Technology

Until now the forecast of the Semmiconductors Industry Association (SIA) concerning the dimension shrinking and the performance improvement of the electrical devices, reported in the International Technology Roadmap for Semiconductors (ITRS), matched very precisely the development of semiconductor process technology. But today the traditional scaling is indeed approaching the fundamental limits of the materials consituting the building blocks of the CMOS process. A big and unresolved challenge in the traditional process shrinking approach is the gate insulator. To be able to follow the dimension shrinking according to the ITRS, the SiO2 film thickness should become below 1nm within the next three years. This thickness corresponds to few atomic layers, which means that the direct tunnel leakage current through the insulator will increase. The high leakage current and the inadequate reliability for a SiO2 layer of less than 1.5nm thickness require a replacement for SiO2. To obtain high gate capacitance and inhibit tunneling, relative thick insulator of high dielectric constant (high-k) are needed to replace silicon dioxide (SiO2) as gate oxide. Therefore new materials have to be introduced into the basic CMOS structure to replace the existing ones to further extend device scaling and the reduction of the produciont costs. The present research thesis focuses on the proposition and investigation of three alternative gate oxide systems: aluminium-, praseodymium- and lanthanum oxide (Al2O3, Pr2O3 and La2O3 respectively). For each one of these systems, the growth process by Molecular Beam Deposition (MBD) has been optimised and electrical and physical characterisation has been performed to gain a better understanding of important factors associated with alternative gate dielectrics form both a theoretical and experimental point of view. Moreover, the optimisation of the interface between gate dielectric and the silicon substrate is taken into account during the development of the deposition processes. The first part of the thesis concerns the aluminium oxide. Aluminium oxide (Al2O3) is one of the first systems which have been studied to replace silicon dioxide as gate dielectric because of its large barrier height, dielectric constant twice that of SiO2, high stability and robustness. The basic properties of Al2O3 films grown on silicon substrate are well understood and for this reason alumina can be used as reference to investigate on new materials for alternative gate oxide. Beyond the aluminium oxide, lanthanide oxides have been considered as long term solution to the high-k question. In particular preseodymium oxide (Pr2O3) and lanthanum oxide (La2O3) have attracted the attention because of their high dielectric constant (20-30) and thermal stability on silicon substrate until 1000K. The properties of thin lanthanide oxide films as dielectric system for microelectronic applications are not yet completely known ind intensive research is running to find out if this dielectric will cover all the requirements needed for the new gate oxide material. In particular the major drawback of lanthanide oxide is given by its high sensibility to humidity, which leads to degradation of the dielectric film. This thesis will try to give an answer to the open questions on the investigated materials and will show the direction for future investigations

Advanced SiC/Oxide Interface Passivation

To save energy on an electric power grid, the idea of redesigned ‘micro-grids’ has been proposed. Implementation of this concept needs power devices that can operate at higher switching speeds and block voltages of up to 20 kV. Out of SiC and GaN wide band gap semiconductors, the former is more suitable for low- as well as high-voltage ranges. SiC exists in different polytypes 3C-, 4H- and 6H-. 4H-SiC due to its wider band gap, 3.26 eV has higher critical electric field of breakdown (Ec) and electron bulk mobility compared to 6H-SiC. Even with all these benefits 4H-SiC full potential has not yet been realized. This is due to high trap densities (Dit) at the interface. In addition to 4H-polytype, in recent years, there is a reignited interest on cubic silicon carbide (3C-SiC), which can be potentially grown heteroepitaxially on 12″ Si substrates, as it would result in a drastic cost reduction of semiconductor devices compared to the successful but exorbitantly expensive SiC hexagonal polytype technology (4H-SiC). In this chapter, we discuss and summarize all different interface passivation techniques or processes that have led to a vast improvement of these (4H- or 3C-SiC/SiO2) interfaces electrically