Quantum-dot Cellular Automata: Review Paper

Quantum-dot Cellular Automata (QCA) is one of the most important discoveries that will be the successful alternative for CMOS technology in the near future. An important feature of this technique, which has attracted the attention of many researchers, is that it is characterized by its low energy consumption, high speed and small size compared with CMOS.  Inverter and majority gate are the basic building blocks for QCA circuits where it can design the most logical circuit using these gates with help of QCA wire. Due to the lack of availability of review papers, this paper will be a destination for many people who are interested in the QCA field and to know how it works and why it had taken lots of attention recentl

New Symmetric and Planar Designs of Reversible Full-Adders/Subtractors in Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies, promising alternative to CMOS technology due to faster speed, smaller size, lower power consumption, higher scale integration and higher switching frequency. Also, power dissipation is the main limitation of all the nano electronics design techniques including the QCA. Researchers have proposed the various mechanisms to limit this problem. Among them, reversible computing is considered as the reliable solution to lower the power dissipation. On the other hand, adders are fundamental circuits for most digital systems. In this paper, Innovation is divided to three sections. In the first section, a method for converting irreversible functions to a reversible one is presented. This method has advantages such as: converting of irreversible functions to reversible one directly and as optimal. So, in this method, sub-optimal methods of using of conventional reversible blocks such as Toffoli and Fredkin are not used, having of minimum number of garbage outputs and so on. Then, Using the method, two new symmetric and planar designs of reversible full-adders are presented. In the second section, a new symmetric, planar and fault tolerant five-input majority gate is proposed. Based on the designed gate, a reversible full-adder are presented. Also, for this gate, a fault-tolerant analysis is proposed. And in the third section, three new 8-bit reversible full-adder/subtractors are designed based on full-adders/subtractors proposed in the second section. The results are indicative of the outperformance of the proposed designs in comparison to the best available ones in terms of area, complexity, delay, reversible/irreversible layout, and also in logic level in terms of garbage outputs, control inputs, number of majority and NOT gates

New Symmetric and Planar Designs of Reversible Full-Adders/Subtractors in Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies, promising alternative to CMOS technology due to faster speed, smaller size, lower power consumption, higher scale integration and higher switching frequency. Also, power dissipation is the main limitation of all the nano electronics design techniques including the QCA. Researchers have proposed the various mechanisms to limit this problem. Among them, reversible computing is considered as the reliable solution to lower the power dissipation. On the other hand, adders are fundamental circuits for most digital systems. In this paper, Innovation is divided to three sections. In the first section, a method for converting irreversible functions to a reversible one is presented. This method has advantages such as: converting of irreversible functions to reversible one directly and as optimal. So, in this method, sub-optimal methods of using of conventional reversible blocks such as Toffoli and Fredkin are not used, having of minimum number of garbage outputs and so on. Then, Using the method, two new symmetric and planar designs of reversible full-adders are presented. In the second section, a new symmetric, planar and fault tolerant five-input majority gate is proposed. Based on the designed gate, a reversible full-adder are presented. Also, for this gate, a fault-tolerant analysis is proposed. And in the third section, three new 8-bit reversible full-adder/subtractors are designed based on full-adders/subtractors proposed in the second section. The results are indicative of the outperformance of the proposed designs in comparison to the best available ones in terms of area, complexity, delay, reversible/irreversible layout, and also in logic level in terms of garbage outputs, control inputs, number of majority and NOT gates

Explorations for Efficient Reversible Barrel Shifters and Their Mappings in QCA Nanocomputing

This thesis is based on promising computing paradigm of reversible logic which generates unique outputs out of the inputs and. Reversible logic circuits maintain one-to-one mapping inside of the inputs and the outputs. Compared to the traditional irreversible computation, reversible logic circuit has the advantage that it successfully avoids the information loss during computations. Also, reversible logic is useful to design ultra-low-power nanocomputing circuits, circuits for quantum computing, and the nanocircuits that are testable in nature. Reversible computing circuits require the ancilla inputs and the garbage outputs. Ancilla input is the constant input in reversible circuits. Garbage output is the output for maintaining the reversibility of the reversible logic but is not any of the primary inputs nor a useful bit. An efficient reversible circuit will have the minimal number of garbage and ancilla bits. Barrel shifter is one of main computing systems having applications in high speed digital signal processing, oating-point arithmetic, FPGA, and Center Processing Unit (CPU). It can operate the function of shifting or rotation for multiple bits in only one clock cycle. The goal of this thesis is to design barrel shifters based on the reversible computing that are optimized in terms of the number of ancilla and garbage bits. In order to achieve this goal, a new Super Conservative Reversible Logic Gate (SCRL gate) has been used. The SCRL gate has 1 control input depending on the value of which it can swap any two n-1 data inputs. We proved that the SCRL gate is superior to the existing conservative reversible Fredkin gate. This thesis develops 5 design methodologies for reversible barrel shifters using SCRL gates that are primarily optimized with the criteria of the number of ancilla and garbage bits. The five proposed methodologies consist of reversible right rotator, reversible logical right shifter, reversible arithmetic right shifter, reversible universal right shifter and reversible universal bidirectional shifter. The proposed reversible barrel shifter design is compared with the existing works in literature and have shown improvement ranging from 8.5% to 92% by the number of garbage and ancilla bits. The SCRL gate and design methodologies of reversible barrel shifter are mapped in Quantum Dot Cellular Automata (QCA) computing. It is illustrated that the SCRL-based designs of reversible barrel shifters have less QCA cost (cost in terms of number of inverters and majority voters) compared to the Fredkin gate- based designs of reversible barrel shifters

Cellular Automata

Modelling and simulation are disciplines of major importance for science and engineering. There is no science without models, and simulation has nowadays become a very useful tool, sometimes unavoidable, for development of both science and engineering. The main attractive feature of cellular automata is that, in spite of their conceptual simplicity which allows an easiness of implementation for computer simulation, as a detailed and complete mathematical analysis in principle, they are able to exhibit a wide variety of amazingly complex behaviour. This feature of cellular automata has attracted the researchers' attention from a wide variety of divergent fields of the exact disciplines of science and engineering, but also of the social sciences, and sometimes beyond. The collective complex behaviour of numerous systems, which emerge from the interaction of a multitude of simple individuals, is being conveniently modelled and simulated with cellular automata for very different purposes. In this book, a number of innovative applications of cellular automata models in the fields of Quantum Computing, Materials Science, Cryptography and Coding, and Robotics and Image Processing are presented

Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results

Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies

Reversible circuits are similar to conventional logic circuits except that they are built from reversible gates. In reversible gates, there is a unique, one-to-one mapping between the inputs and outputs, not the case with conventional logic. Also, reversible gates require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Reversible circuits hold promise in futuristic computing technologies like quantum computing, quantum dot cellular automata, DNA computing, optical computing, etc. Thus, it is important to minimize parameters such as ancilla and garbage bits, quantum cost and delay in the design of reversible circuits. The first contribution of this dissertation is the design of a new reversible gate namely the TR gate (Thapliyal-Ranganathan) which has the unique structure that makes it ideal for the realization of arithmetic circuits such as adders, subtractors and comparators, efficient in terms of the parameters such as ancilla and garbage bits, quantum cost and delay. The second contribution is the development of design methodologies and a synthesis framework to synthesize reversible data path functional units, such as binary and BCD adders, subtractors, adder-subtractors and binary comparators. The objective behind the proposed design methodologies is to synthesize arithmetic and logic functional units optimizing key metrics such as ancilla inputs, garbage outputs, quantum cost and delay. A library of reversible gates such as the Fredkin gate, the Toffoli gate, the TR gate, etc. was developed by coding in Verilog for use during synthesis. The third contribution of this dissertation is the set of methodologies for the design of reversible sequential circuits such as reversible latches, flip-flops and shift registers. The reversible designs of asynchronous set/reset D latch and the D flip-flop are attempted for the first time. It is shown that the designs are optimal in terms of number of garbage outputs while exploring the best possible values for quantum cost and delay. The other important contributions of this dissertation are the applications of reversible logic as well as a special class of reversible logic called conservative reversible logic towards concurrent (online) and offline testing of single as well as multiple faults in traditional and reversible nanoscale VLSI circuits, based on emerging nanotechnologies such as QCA, quantum computing, etc. Nanoelectronic devices tend to have high permanent and transient faults and thus are susceptible to high error rates. Specific contributions include (i) concurrently testable sequential circuits for molecular QCA based on reversible logic, (ii) concurrently testable QCA-based FPGA, (iii) design of self checking conservative logic gates for QCA, (iv) concurrent multiple error detection in emerging nanotechnologies using reversible logic, (v) two-vectors, all 0s and all 1s, testable reversible sequential circuits

Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies

Reversible circuits are similar to conventional logic circuits except that they are built from reversible gates. In reversible gates, there is a unique, one-to-one mapping between the inputs and outputs, not the case with conventional logic. Also, reversible gates require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Reversible circuits hold promise in futuristic computing technologies like quantum computing, quantum dot cellular automata, DNA computing, optical computing, etc. Thus, it is important to minimize parameters such as ancilla and garbage bits, quantum cost and delay in the design of reversible circuits. The first contribution of this dissertation is the design of a new reversible gate namely the TR gate (Thapliyal-Ranganathan) which has the unique structure that makes it ideal for the realization of arithmetic circuits such as adders, subtractors and comparators, efficient in terms of the parameters such as ancilla and garbage bits, quantum cost and delay. The second contribution is the development of design methodologies and a synthesis framework to synthesize reversible data path functional units, such as binary and BCD adders, subtractors, adder-subtractors and binary comparators. The objective behind the proposed design methodologies is to synthesize arithmetic and logic functional units optimizing key metrics such as ancilla inputs, garbage outputs, quantum cost and delay. A library of reversible gates such as the Fredkin gate, the Toffoli gate, the TR gate, etc. was developed by coding in Verilog for use during synthesis. The third contribution of this dissertation is the set of methodologies for the design of reversible sequential circuits such as reversible latches, flip-flops and shift registers. The reversible designs of asynchronous set/reset D latch and the D flip-flop are attempted for the first time. It is shown that the designs are optimal in terms of number of garbage outputs while exploring the best possible values for quantum cost and delay. The other important contributions of this dissertation are the applications of reversible logic as well as a special class of reversible logic called conservative reversible logic towards concurrent (online) and offline testing of single as well as multiple faults in traditional and reversible nanoscale VLSI circuits, based on emerging nanotechnologies such as QCA, quantum computing, etc. Nanoelectronic devices tend to have high permanent and transient faults and thus are susceptible to high error rates. Specific contributions include (i) concurrently testable sequential circuits for molecular QCA based on reversible logic, (ii) concurrently testable QCA-based FPGA, (iii) design of self checking conservative logic gates for QCA, (iv) concurrent multiple error detection in emerging nanotechnologies using reversible logic, (v) two-vectors, all 0s and all 1s, testable reversible sequential circuits