Bayesian inference in neural circuits and synapses

Bayesian inference describes how to reason optimally under uncertainty. As the brain faces considerable uncertainty, it may be possible to understand aspects of neural computation using Bayesian inference. In this thesis, I address several questions within this broad theme. First, I show that con dence reports may, in some circumstances be Bayes optimal, by taking a \doubly Bayesian" strategy: computing the Bayesian model evidence for several di erent models of participant's behaviour, one of which is itself Bayesian. Second, I address a related question concerning features of the probability distributions realised by neural activity. In particular, it has been show that neural activity obeys Zipf's law, as do many other statistical distributions. We show the emergence of Zipf's law is in fact unsurprising, as it emerges from the existence of an underlying latent variable: ring rate. Third, I show that synaptic plasticity can be formulated as a Bayesian inference problem, and I give neural evidence in support of this proposition, based on the hypothesis that neurons sample from the resulting posterior distributions. Fourth, I consider how oscillatory excitatory-inhibitory circuits might perform inference by relating these circuits to a highly effective method for probabilistic inference: Hamiltonian Monte Carlo

SpiNNaker - A Spiking Neural Network Architecture

20 years in conception and 15 in construction, the SpiNNaker project has delivered the world’s largest neuromorphic computing platform incorporating over a million ARM mobile phone processors and capable of modelling spiking neural networks of the scale of a mouse brain in biological real time. This machine, hosted at the University of Manchester in the UK, is freely available under the auspices of the EU Flagship Human Brain Project. This book tells the story of the origins of the machine, its development and its deployment, and the immense software development effort that has gone into making it openly available and accessible to researchers and students the world over. It also presents exemplar applications from ‘Talk’, a SpiNNaker-controlled robotic exhibit at the Manchester Art Gallery as part of ‘The Imitation Game’, a set of works commissioned in 2016 in honour of Alan Turing, through to a way to solve hard computing problems using stochastic neural networks. The book concludes with a look to the future, and the SpiNNaker-2 machine which is yet to come

Circuit techniques for low-voltage and high-speed A/D converters

The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage. Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented. It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes. An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering. The throughput of ADCs can be increased by using parallelism. This is demonstrated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.reviewe

94 GHz Monolithic Transmitter for Weather Radar Application

This thesis was written for concluding my studies at the University of Padua. The main topic is the design of a monolithic transmitter in SiGe bipolar technology, for weather radar application at an operating frequency around 94GHz. At such a high frequency parasitic elements have to be taken into account very carefully. Appropriate matching networks become important to allow the signals to pass across the different ections of the transmitter, without reflections or attenuations. To this aim, transmission lines were used instead of inductors, in order to save size and to have a more reliable modelling of device parameters and parasitic elements. The structure of the transmitter includes a transformer (which acts as Balun), a frequency quadrupler and a buffer. The transmitter input receives a single-ended reference signal at 23.5GHz, with a power of 0dBm on a single-ended input impedance of 50Ω. The output has been designed for a differential load of 100Ω and to operate in the temperature range of 0°C - 100°C, with a typical output power above 10dBm and spurious harmonic below -25dBcopenMotivi di sicurezza e/o proprietà dei risultati e/o informazioni sensibil

SpiNNaker - A Spiking Neural Network Architecture

20 years in conception and 15 in construction, the SpiNNaker project has delivered the world’s largest neuromorphic computing platform incorporating over a million ARM mobile phone processors and capable of modelling spiking neural networks of the scale of a mouse brain in biological real time. This machine, hosted at the University of Manchester in the UK, is freely available under the auspices of the EU Flagship Human Brain Project. This book tells the story of the origins of the machine, its development and its deployment, and the immense software development effort that has gone into making it openly available and accessible to researchers and students the world over. It also presents exemplar applications from ‘Talk’, a SpiNNaker-controlled robotic exhibit at the Manchester Art Gallery as part of ‘The Imitation Game’, a set of works commissioned in 2016 in honour of Alan Turing, through to a way to solve hard computing problems using stochastic neural networks. The book concludes with a look to the future, and the SpiNNaker-2 machine which is yet to come

when channels cooperate or capacitance varies

Die elektrische Signalverarbeitung in Nervenzellen basiert auf deren erregbarer Zellmembran. Üblicherweise wird angenommen, dass die in der Membran eingebetteten leitfähigen Ionenkanäle nicht auf direkte Art gekoppelt sind und dass die Kapazität des von der Membran gebildeten Kondensators konstant ist. Allerdings scheinen diese Annahmen nicht für alle Nervenzellen zu gelten. Im Gegenteil, verschiedene Ionenkanäle “kooperieren” und auch die Vorstellung von einer konstanten spezifischen Membrankapazität wurde kürzlich in Frage gestellt. Die Auswirkungen dieser Abweichungen auf die elektrischen Eigenschaften von Nervenzellen ist das Thema der folgenden kumulativen Dissertationsschrift. Im ersten Projekt wird gezeigt, auf welche Weise stark kooperative spannungsabhängige Ionenkanäle eine Form von zellulärem Kurzzeitspeicher für elektrische Aktivität bilden könnten. Solche kooperativen Kanäle treten in der Membran häufig in kleinen räumlich getrennte Clustern auf. Basierend auf einem mathematischen Modell wird nachgewiesen, dass solche Kanalcluster als eine bistabile Leitfähigkeit agieren. Die dadurch entstehende große Speicherkapazität eines Ensembles dieser Kanalcluster könnte von Nervenzellen für stufenloses persistentes Feuern genutzt werden -- ein Feuerverhalten von Nutzen für das Kurzzeichgedächtnis. Im zweiten Projekt wird ein neues Dynamic Clamp Protokoll entwickelt, der Capacitance Clamp, das erlaubt, Änderungen der Membrankapazität in biologischen Nervenzellen zu emulieren. Eine solche experimentelle Möglichkeit, um systematisch die Rolle der Kapazität zu untersuchen, gab es bisher nicht. Nach einer Reihe von Tests in Simulationen und Experimenten wurde die Technik mit Körnerzellen des *Gyrus dentatus* genutzt, um den Einfluss von Kapazität auf deren Feuerverhalten zu studieren. Die Kombination beider Projekte zeigt die Relevanz dieser oft vernachlässigten Facetten von neuronalen Membranen für die Signalverarbeitung in Nervenzellen.Electrical signaling in neurons is shaped by their specialized excitable cell membranes. Commonly, it is assumed that the ion channels embedded in the membrane gate independently and that the electrical capacitance of neurons is constant. However, not all excitable membranes appear to adhere to these assumptions. On the contrary, ion channels are observed to gate cooperatively in several circumstances and also the notion of one fixed value for the specific membrane capacitance (per unit area) across neuronal membranes has been challenged recently. How these deviations from the original form of conductance-based neuron models affect their electrical properties has not been extensively explored and is the focus of this cumulative thesis. In the first project, strongly cooperative voltage-gated ion channels are proposed to provide a membrane potential-based mechanism for cellular short-term memory. Based on a mathematical model of cooperative gating, it is shown that coupled channels assembled into small clusters act as an ensemble of bistable conductances. The correspondingly large memory capacity of such an ensemble yields an alternative explanation for graded forms of cell-autonomous persistent firing – an observed firing mode implicated in working memory. In the second project, a novel dynamic clamp protocol -- the capacitance clamp -- is developed to artificially modify capacitance in biological neurons. Experimental means to systematically investigate capacitance, a basic parameter shared by all excitable cells, had previously been missing. The technique, thoroughly tested in simulations and experiments, is used to monitor how capacitance affects temporal integration and energetic costs of spiking in dentate gyrus granule cells. Combined, the projects identify computationally relevant consequences of these often neglected facets of neuronal membranes and extend the modeling and experimental techniques to further study them