7 research outputs found
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Concatenated LDPC-TCM coding for reliable storage in multi-level flash memories
In this paper, we present an efficient fault tolerant solution for multi-level per cell (MLC) flash memory that concatenates trellis coded modulation (TCM) with an outer low-density parity-check (LDPC) code. Traditional flash coding systems employ simple hard-decisions based codes, such as Bose-Chaudhuri-Hocquenghem (BCH) codes, that can correct a fixed, specified number of errors. Thanks to the Bahl, Cocke, Jelinek, and Raviv (BCJR) algorithm, the TCM decoder within the proposed design can provide soft decisions which make it possible to use the more powerful LDPC codes. Moreover, the error-correction performance is further improved since TCM can decrease the raw error rate of MLC and hence relieve the burden of outer LDPC code. The effectiveness of concatenated LDPC-TCM systems has been successfully demonstrated through computer simulations
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Data reliability and error correction for NAND Flash Memory System
NAND flash memory has been widely used for data storage due to its high density, high throughput, and low power. However, as the flash memory scales to smaller process technologies and stores more bits per cell, its reliability is decreasing. The error correction coding can be used to significantly improve the data reliability; nevertheless, the advanced ECCs such as low-density parity-check (LDPC) codes generally demand soft decisions while NAND flash memory channel provides hard-decisions only. Extracting the soft information requires the accurate characterization of flash memory channel and the effective design of coding schemes.
To this end, we have presented a novel LDPC-TCM coding scheme for the Multilevel Cell (MLC) flash memories. The a posteriori TCM decoding algorithm is used in the scheme to generate soft information, which is fed to the LDPC decoder for further correction of data bits. It has been demonstrated that the proposed scheme can achieve higher error correction performance than the traditional hard-decisions based flash coding algorithms, and is feasible in the design practice. Further with the LDPC-TCM, we believe it is important to characterize the flash memory channel and investigate a method to calculate the soft decision for each bit, with the available channel outputs. We studied the various noises and interferences occurring in the memory channel and mathematically formulated the probability density function of the overall noise distribution. Based on the results we derived the final distribution for the cell threshold voltages, which can be used to instruct the calculation of soft decisions. The discoveries on the theoretical level have been demonstrated to be consistent with the real channel behaviours. The channel characterization and model provided in this dissertation can enable more design of soft-decisions based ECCs for future NAND flash memories.
The data pattern processing algorithm deals with the write patterns and targets to lower the proportion of patterns that would introduce data errors. On the other hand, the voltages applied to the memory cells charges the MOSFET capacitances frequently on programming these data patterns, leading to the power problem. The high energy consumption and current spikes also cause reliability issue to the data stored in the flash memory. This dissertation proposes a write pattern formatting algorithm (WPFA) attempting to solve the two problems together. We have designed and implemented the algorithm and evaluated its performance through both the software simulations and hardware synthesis
ΠΠ½Π°Π»ΠΈΠ· ΡΡΡΠ΅ΠΊΡΠΈΠ²Π½ΠΎΡΡΠΈ ΠΊΠ°ΡΠΊΠ°Π΄Π½ΠΎΠ³ΠΎ ΠΊΠΎΠ΄ΠΈΡΠΎΠ²Π°Π½ΠΈΡ Π΄Π»Ρ ΠΏΠΎΠ²ΡΡΠ΅Π½ΠΈΡ Π²ΡΠ½ΠΎΡΠ»ΠΈΠ²ΠΎΡΡΠΈ ΠΌΠ½ΠΎΠ³ΠΎΡΡΠΎΠ²Π½Π΅Π²ΠΎΠΉ NAND ΡΠ»Π΅Ρ-ΠΏΠ°ΠΌΡΡΠΈ
The increasing storage density of modern NAND flash memory chips, achieved both due to scaling down the cell size, and due to the increasing number of used cell states, leads to a decrease in data storage reliability, namely, error probability, endurance (number of P/E cycling) and retention time. Error correction codes are often used to improve the reliability of data storage in multilevel flash memory. The effectiveness of using error correction codes is largely determined by the model accuracy that exhibits the basic processes associated with writing and reading data. The paper describes the main sources of disturbances for a flash cell that affect the threshold voltage of the cell in NAND flash memory, and represents an explicit form of the threshold voltage distribution. As an approximation of the obtained threshold voltage distribution, a Normal-Laplace mixture model was shown to be a good fit in multilevel flash memories for a large number of rewriting cycles. For this model, a performance analysis of the concatenated coding scheme with an outer Reed-Solomon code and an inner multilevel code consisting of binary component codes is carried out. The performed analysis makes it possible to obtain tradeoffs between the error probability, storage density, and the number of P/E cycling. The resulting tradeoffs show that the considered concatenated coding schemes allow, due to a very slight decrease in the storage density, to increase the number of P/E cycling up to 2β2.5 times than their nominal endurance specification while maintaining the required value of the bit error probability.ΠΠΎΠ²ΡΡΠ΅Π½ΠΈΠ΅ ΠΏΠ»ΠΎΡΠ½ΠΎΡΡΠΈ Π·Π°ΠΏΠΈΡΠΈ Π² ΡΠΎΠ²ΡΠ΅ΠΌΠ΅Π½Π½ΡΡ
ΡΠΈΠΏΠ°Ρ
NAND ΡΠ»Π΅Ρ-ΠΏΠ°ΠΌΡΡΠΈ, Π΄ΠΎΡΡΠΈΠ³Π°Π΅ΠΌΠΎΠ΅ ΠΊΠ°ΠΊ Π·Π° ΡΡΠ΅Ρ ΡΠΌΠ΅Π½ΡΡΠ°ΡΡΠ΅Π³ΠΎΡΡ ΡΠΈΠ·ΠΈΡΠ΅ΡΠΊΠΎΠ³ΠΎ ΡΠ°Π·ΠΌΠ΅ΡΠ° ΡΡΠ΅ΠΉΠΊΠΈ, ΡΠ°ΠΊ ΠΈ Π±Π»Π°Π³ΠΎΠ΄Π°ΡΡ Π²ΠΎΠ·ΡΠ°ΡΡΠ°ΡΡΠ΅ΠΌΡ ΠΊΠΎΠ»ΠΈΡΠ΅ΡΡΠ²Ρ ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΠ΅ΠΌΡΡ
ΡΠΎΡΡΠΎΡΠ½ΠΈΠΉ ΡΡΠ΅ΠΉΠΊΠΈ, ΡΠΎΠΏΡΠΎΠ²ΠΎΠΆΠ΄Π°Π΅ΡΡΡ ΡΠ½ΠΈΠΆΠ΅Π½ΠΈΠ΅ΠΌ Π½Π°Π΄Π΅ΠΆΠ½ΠΎΡΡΠΈ Ρ
ΡΠ°Π½Π΅Π½ΠΈΡ Π΄Π°Π½Π½ΡΡ
β Π²Π΅ΡΠΎΡΡΠ½ΠΎΡΡΠΈ ΠΎΡΠΈΠ±ΠΊΠΈ, Π²ΡΠ½ΠΎΡΠ»ΠΈΠ²ΠΎΡΡΠΈ (ΡΠΈΡΠ»Π° ΡΠΈΠΊΠ»ΠΎΠ² ΠΏΠ΅ΡΠ΅Π·Π°ΠΏΠΈΡΠΈ) ΠΈ Π²ΡΠ΅ΠΌΠ΅Π½ΠΈ Ρ
ΡΠ°Π½Π΅Π½ΠΈΡ. Π‘ΡΠ°Π½Π΄Π°ΡΡΠ½ΡΠΌ ΡΠ΅ΡΠ΅Π½ΠΈΠ΅ΠΌ, ΠΏΠΎΠ·Π²ΠΎΠ»ΡΡΡΠΈΠΌ ΠΏΠΎΠ²ΡΡΠΈΡΡ Π½Π°Π΄Π΅ΠΆΠ½ΠΎΡΡΡ Ρ
ΡΠ°Π½Π΅Π½ΠΈΡ Π΄Π°Π½Π½ΡΡ
Π² ΠΌΠ½ΠΎΠ³ΠΎΡΡΠΎΠ²Π½Π΅Π²ΠΎΠΉ ΡΠ»Π΅Ρ-ΠΏΠ°ΠΌΡΡΠΈ, ΡΠ²Π»ΡΠ΅ΡΡΡ Π²Π²Π΅Π΄Π΅Π½ΠΈΠ΅ ΠΏΠΎΠΌΠ΅Ρ
ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΠΎΠ³ΠΎ ΠΊΠΎΠ΄ΠΈΡΠΎΠ²Π°Π½ΠΈΡ. ΠΡΡΠ΅ΠΊΡΠΈΠ²Π½ΠΎΡΡΡ Π²Π²Π΅Π΄Π΅Π½ΠΈΡ ΠΏΠΎΠΌΠ΅Ρ
ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΠΎΠ³ΠΎ ΠΊΠΎΠ΄ΠΈΡΠΎΠ²Π°Π½ΠΈΡ Π² ΡΡΡΠ΅ΡΡΠ²Π΅Π½Π½ΠΎΠΉ ΡΡΠ΅ΠΏΠ΅Π½ΠΈ ΠΎΠΏΡΠ΅Π΄Π΅Π»ΡΠ΅ΡΡΡ Π°Π΄Π΅ΠΊΠ²Π°ΡΠ½ΠΎΡΡΡΡ ΠΌΠΎΠ΄Π΅Π»ΠΈ, ΡΠΎΡΠΌΠ°Π»ΠΈΠ·ΡΡΡΠ΅ΠΉ ΠΎΡΠ½ΠΎΠ²Π½ΡΠ΅ ΠΏΡΠΎΡΠ΅ΡΡΡ, ΡΠ²ΡΠ·Π°Π½Π½ΡΠ΅ Ρ Π·Π°ΠΏΠΈΡΡΡ ΠΈ ΡΡΠ΅Π½ΠΈΠ΅ΠΌ Π΄Π°Π½Π½ΡΡ
. Π ΡΠ°Π±ΠΎΡΠ΅ ΠΏΡΠΈΠ²ΠΎΠ΄ΠΈΡΡΡ ΠΎΠΏΠΈΡΠ°Π½ΠΈΠ΅ ΠΎΡΠ½ΠΎΠ²Π½ΡΡ
ΠΈΡΠΊΠ°ΠΆΠ΅Π½ΠΈΠΉ, ΡΠΎΠΏΡΠΎΠ²ΠΎΠΆΠ΄Π°ΡΡΠΈΡ
ΠΏΡΠΎΡΠ΅ΡΡ Π·Π°ΠΏΠΈΡΠΈ/ΡΡΠΈΡΡΠ²Π°Π½ΠΈΡ Π² NAND ΡΠ»Π΅Ρ-ΠΏΠ°ΠΌΡΡΠΈ, ΠΈ ΡΠ²Π½ΡΠΉ Π²ΠΈΠ΄ ΠΏΠ»ΠΎΡΠ½ΠΎΡΡΠ΅ΠΉ ΡΠ°ΡΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΡΠ΅Π·ΡΠ»ΡΡΠΈΡΡΡΡΠ΅Π³ΠΎ ΡΡΠΌΠ°. Π ΠΊΠ°ΡΠ΅ΡΡΠ²Π΅ Π°ΠΏΠΏΡΠΎΠΊΡΠΈΠΌΠ°ΡΠΈΠΈ ΠΏΠΎΠ»ΡΡΠ΅Π½Π½ΡΡ
ΠΏΠ»ΠΎΡΠ½ΠΎΡΡΠ΅ΠΉ ΡΠ°ΡΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΡΠ΅Π·ΡΠ»ΡΡΠΈΡΡΡΡΠ΅Π³ΠΎ ΡΡΠΌΠ° ΡΠ°ΡΡΠΌΠ°ΡΡΠΈΠ²Π°Π΅ΡΡΡ ΠΌΠΎΠ΄Π΅Π»Ρ Π½Π° ΠΎΡΠ½ΠΎΠ²Π΅ ΠΊΠΎΠΌΠΏΠΎΠ·ΠΈΡΠΈΠΈ Π³Π°ΡΡΡΠΎΠ²Π° ΡΠ°ΡΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΠΈ ΡΠ°ΡΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΠΠ°ΠΏΠ»Π°ΡΠ°, Π΄ΠΎΡΡΠ°ΡΠΎΡΠ½ΠΎ Π°Π΄Π΅ΠΊΠ²Π°ΡΠ½ΠΎ ΠΎΡΡΠ°ΠΆΠ°ΡΡΠ°Ρ ΠΏΠ»ΠΎΡΠ½ΠΎΡΡΠΈ ΡΠ°ΡΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΡΠ΅Π·ΡΠ»ΡΡΠΈΡΡΡΡΠ΅Π³ΠΎ ΡΡΠΌΠ° ΠΏΡΠΈ Π±ΠΎΠ»ΡΡΠΎΠΌ ΡΠΈΡΠ»Π΅ ΡΠΈΠΊΠ»ΠΎΠ² ΠΏΠ΅ΡΠ΅Π·Π°ΠΏΠΈΡΠΈ. ΠΠ»Ρ ΡΡΠΎΠΉ ΠΌΠΎΠ΄Π΅Π»ΠΈ ΠΏΡΠΎΠ²ΠΎΠ΄ΠΈΡΡΡ Π°Π½Π°Π»ΠΈΠ· ΠΏΠΎΠΌΠ΅Ρ
ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΠΎΡΡΠΈ ΠΊΠ°ΡΠΊΠ°Π΄Π½ΡΡ
ΠΊΠΎΠ΄ΠΎΠ²ΡΡ
ΠΊΠΎΠ½ΡΡΡΡΠΊΡΠΈΠΉ Ρ Π²Π½Π΅ΡΠ½ΠΈΠΌ ΠΊΠΎΠ΄ΠΎΠΌ Π ΠΈΠ΄Π°-Π‘ΠΎΠ»ΠΎΠΌΠΎΠ½Π° ΠΈ Π²Π½ΡΡΡΠ΅Π½Π½ΠΈΠΌ ΠΌΠ½ΠΎΠ³ΠΎΡΡΠΎΠ²Π½Π΅Π²ΡΠΌ ΠΊΠΎΠ΄ΠΎΠΌ, ΡΠΎΡΡΠΎΡΡΠΈΠΌ ΠΈΠ· Π΄Π²ΠΎΠΈΡΠ½ΡΡ
ΠΊΠΎΠΌΠΏΠΎΠ½Π΅Π½ΡΠ½ΡΡ
ΠΊΠΎΠ΄ΠΎΠ². ΠΡΠΏΠΎΠ»Π½Π΅Π½Π½ΡΠΉ Π°Π½Π°Π»ΠΈΠ· ΠΏΠΎΠ·Π²ΠΎΠ»ΡΠ΅Ρ ΠΏΠΎΠ»ΡΡΠΈΡΡ ΠΎΠ±ΠΌΠ΅Π½Π½ΡΠ΅ ΡΠΎΠΎΡΠ½ΠΎΡΠ΅Π½ΠΈΡ ΠΌΠ΅ΠΆΠ΄Ρ Π²Π΅ΡΠΎΡΡΠ½ΠΎΡΡΡΡ ΠΎΡΠΈΠ±ΠΊΠΈ, ΠΏΠ»ΠΎΡΠ½ΠΎΡΡΡΡ Π·Π°ΠΏΠΈΡΠΈ ΠΈ ΡΠΈΡΠ»ΠΎΠΌ ΡΠΈΠΊΠ»ΠΎΠ² ΠΏΠ΅ΡΠ΅Π·Π°ΠΏΠΈΡΠΈ. ΠΠΎΠ»ΡΡΠ΅Π½Π½ΡΠ΅ ΠΎΠ±ΠΌΠ΅Π½Π½ΡΠ΅ ΡΠΎΠΎΡΠ½ΠΎΡΠ΅Π½ΠΈΡ ΠΏΠΎΠΊΠ°Π·ΡΠ²Π°ΡΡ, ΡΡΠΎ ΠΏΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½Π½ΡΠ΅ ΠΊΠΎΠ½ΡΡΡΡΠΊΡΠΈΠΈ ΠΏΠΎΠ·Π²ΠΎΠ»ΡΡΡ Π·Π° ΡΡΠ΅Ρ ΠΎΡΠ΅Π½Ρ Π½Π΅Π·Π½Π°ΡΠΈΡΠ΅Π»ΡΠ½ΠΎΠ³ΠΎ ΡΠ½ΠΈΠΆΠ΅Π½ΠΈΡ ΠΏΠ»ΠΎΡΠ½ΠΎΡΡΠΈ Π·Π°ΠΏΠΈΡΠΈ ΠΎΠ±Π΅ΡΠΏΠ΅ΡΠΈΡΡ ΡΠ²Π΅Π»ΠΈΡΠ΅Π½ΠΈΠ΅ Π³ΡΠ°Π½ΠΈΡΠ½ΠΎΠ³ΠΎ Π·Π½Π°ΡΠ΅Π½ΠΈΡ ΡΠΈΡΠ»Π° ΡΠΈΠΊΠ»ΠΎΠ² ΠΏΠ΅ΡΠ΅Π·Π°ΠΏΠΈΡΠΈ (ΠΎΠΏΡΠ΅Π΄Π΅Π»ΡΠ΅ΠΌΠΎΠ³ΠΎ ΠΏΡΠΎΠΈΠ·Π²ΠΎΠ΄ΠΈΡΠ΅Π»Π΅ΠΌ) Π² 2β2.5 ΡΠ°Π·Π° ΠΏΡΠΈ ΡΠΎΡ
ΡΠ°Π½Π΅Π½ΠΈΠΈ ΡΡΠ΅Π±ΡΠ΅ΠΌΠΎΠ³ΠΎ Π·Π½Π°ΡΠ΅Π½ΠΈΡ Π²Π΅ΡΠΎΡΡΠ½ΠΎΡΡΠΈ ΠΎΡΠΈΠ±ΠΊΠΈ Π½Π° Π±ΠΈΡ
ΠΠ½Π°Π»ΠΈΠ· ΡΡΡΠ΅ΠΊΡΠΈΠ²Π½ΠΎΡΡΠΈ ΠΊΠ°ΡΠΊΠ°Π΄Π½ΠΎΠ³ΠΎ ΠΊΠΎΠ΄ΠΈΡΠΎΠ²Π°Π½ΠΈΡ Π΄Π»Ρ ΠΏΠΎΠ²ΡΡΠ΅Π½ΠΈΡ Π²ΡΠ½ΠΎΡΠ»ΠΈΠ²ΠΎΡΡΠΈ ΠΌΠ½ΠΎΠ³ΠΎΡΡΠΎΠ²Π½Π΅Π²ΠΎΠΉ NAND ΡΠ»Π΅Ρ-ΠΏΠ°ΠΌΡΡΠΈ
ΠΠΎΠ²ΡΡΠ΅Π½ΠΈΠ΅ ΠΏΠ»ΠΎΡΠ½ΠΎΡΡΠΈ Π·Π°ΠΏΠΈΡΠΈ Π² ΡΠΎΠ²ΡΠ΅ΠΌΠ΅Π½Π½ΡΡ
ΡΠΈΠΏΠ°Ρ
NAND ΡΠ»Π΅Ρ-ΠΏΠ°ΠΌΡΡΠΈ, Π΄ΠΎΡΡΠΈΠ³Π°Π΅ΠΌΠΎΠ΅ ΠΊΠ°ΠΊ Π·Π° ΡΡΠ΅Ρ ΡΠΌΠ΅Π½ΡΡΠ°ΡΡΠ΅Π³ΠΎΡΡ ΡΠΈΠ·ΠΈΡΠ΅ΡΠΊΠΎΠ³ΠΎ ΡΠ°Π·ΠΌΠ΅ΡΠ° ΡΡΠ΅ΠΉΠΊΠΈ, ΡΠ°ΠΊ ΠΈ Π±Π»Π°Π³ΠΎΠ΄Π°ΡΡ Π²ΠΎΠ·ΡΠ°ΡΡΠ°ΡΡΠ΅ΠΌΡ ΠΊΠΎΠ»ΠΈΡΠ΅ΡΡΠ²Ρ ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΠ΅ΠΌΡΡ
ΡΠΎΡΡΠΎΡΠ½ΠΈΠΉ ΡΡΠ΅ΠΉΠΊΠΈ, ΡΠΎΠΏΡΠΎΠ²ΠΎΠΆΠ΄Π°Π΅ΡΡΡ ΡΠ½ΠΈΠΆΠ΅Π½ΠΈΠ΅ΠΌ Π½Π°Π΄Π΅ΠΆΠ½ΠΎΡΡΠΈ Ρ
ΡΠ°Π½Π΅Π½ΠΈΡ Π΄Π°Π½Π½ΡΡ
β Π²Π΅ΡΠΎΡΡΠ½ΠΎΡΡΠΈ ΠΎΡΠΈΠ±ΠΊΠΈ, Π²ΡΠ½ΠΎΡΠ»ΠΈΠ²ΠΎΡΡΠΈ (ΡΠΈΡΠ»Π° ΡΠΈΠΊΠ»ΠΎΠ² ΠΏΠ΅ΡΠ΅Π·Π°ΠΏΠΈΡΠΈ) ΠΈ Π²ΡΠ΅ΠΌΠ΅Π½ΠΈ Ρ
ΡΠ°Π½Π΅Π½ΠΈΡ. Π‘ΡΠ°Π½Π΄Π°ΡΡΠ½ΡΠΌ ΡΠ΅ΡΠ΅Π½ΠΈΠ΅ΠΌ, ΠΏΠΎΠ·Π²ΠΎΠ»ΡΡΡΠΈΠΌ ΠΏΠΎΠ²ΡΡΠΈΡΡ Π½Π°Π΄Π΅ΠΆΠ½ΠΎΡΡΡ Ρ
ΡΠ°Π½Π΅Π½ΠΈΡ Π΄Π°Π½Π½ΡΡ
Π² ΠΌΠ½ΠΎΠ³ΠΎΡΡΠΎΠ²Π½Π΅Π²ΠΎΠΉ ΡΠ»Π΅Ρ-ΠΏΠ°ΠΌΡΡΠΈ, ΡΠ²Π»ΡΠ΅ΡΡΡ Π²Π²Π΅Π΄Π΅Π½ΠΈΠ΅ ΠΏΠΎΠΌΠ΅Ρ
ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΠΎΠ³ΠΎ ΠΊΠΎΠ΄ΠΈΡΠΎΠ²Π°Π½ΠΈΡ. ΠΡΡΠ΅ΠΊΡΠΈΠ²Π½ΠΎΡΡΡ Π²Π²Π΅Π΄Π΅Π½ΠΈΡ ΠΏΠΎΠΌΠ΅Ρ
ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΠΎΠ³ΠΎ ΠΊΠΎΠ΄ΠΈΡΠΎΠ²Π°Π½ΠΈΡ Π² ΡΡΡΠ΅ΡΡΠ²Π΅Π½Π½ΠΎΠΉ ΡΡΠ΅ΠΏΠ΅Π½ΠΈ ΠΎΠΏΡΠ΅Π΄Π΅Π»ΡΠ΅ΡΡΡ Π°Π΄Π΅ΠΊΠ²Π°ΡΠ½ΠΎΡΡΡΡ ΠΌΠΎΠ΄Π΅Π»ΠΈ, ΡΠΎΡΠΌΠ°Π»ΠΈΠ·ΡΡΡΠ΅ΠΉ ΠΎΡΠ½ΠΎΠ²Π½ΡΠ΅ ΠΏΡΠΎΡΠ΅ΡΡΡ, ΡΠ²ΡΠ·Π°Π½Π½ΡΠ΅ Ρ Π·Π°ΠΏΠΈΡΡΡ ΠΈ ΡΡΠ΅Π½ΠΈΠ΅ΠΌ Π΄Π°Π½Π½ΡΡ
. Π ΡΠ°Π±ΠΎΡΠ΅ ΠΏΡΠΈΠ²ΠΎΠ΄ΠΈΡΡΡ ΠΎΠΏΠΈΡΠ°Π½ΠΈΠ΅ ΠΎΡΠ½ΠΎΠ²Π½ΡΡ
ΠΈΡΠΊΠ°ΠΆΠ΅Π½ΠΈΠΉ, ΡΠΎΠΏΡΠΎΠ²ΠΎΠΆΠ΄Π°ΡΡΠΈΡ
ΠΏΡΠΎΡΠ΅ΡΡ Π·Π°ΠΏΠΈΡΠΈ/ΡΡΠΈΡΡΠ²Π°Π½ΠΈΡ Π² NAND ΡΠ»Π΅Ρ-ΠΏΠ°ΠΌΡΡΠΈ, ΠΈ ΡΠ²Π½ΡΠΉ Π²ΠΈΠ΄ ΠΏΠ»ΠΎΡΠ½ΠΎΡΡΠ΅ΠΉ ΡΠ°ΡΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΡΠ΅Π·ΡΠ»ΡΡΠΈΡΡΡΡΠ΅Π³ΠΎ ΡΡΠΌΠ°. Π ΠΊΠ°ΡΠ΅ΡΡΠ²Π΅ Π°ΠΏΠΏΡΠΎΠΊΡΠΈΠΌΠ°ΡΠΈΠΈ ΠΏΠΎΠ»ΡΡΠ΅Π½Π½ΡΡ
ΠΏΠ»ΠΎΡΠ½ΠΎΡΡΠ΅ΠΉ ΡΠ°ΡΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΡΠ΅Π·ΡΠ»ΡΡΠΈΡΡΡΡΠ΅Π³ΠΎ ΡΡΠΌΠ° ΡΠ°ΡΡΠΌΠ°ΡΡΠΈΠ²Π°Π΅ΡΡΡ ΠΌΠΎΠ΄Π΅Π»Ρ Π½Π° ΠΎΡΠ½ΠΎΠ²Π΅ ΠΊΠΎΠΌΠΏΠΎΠ·ΠΈΡΠΈΠΈ Π³Π°ΡΡΡΠΎΠ²Π° ΡΠ°ΡΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΠΈ ΡΠ°ΡΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΠΠ°ΠΏΠ»Π°ΡΠ°, Π΄ΠΎΡΡΠ°ΡΠΎΡΠ½ΠΎ Π°Π΄Π΅ΠΊΠ²Π°ΡΠ½ΠΎ ΠΎΡΡΠ°ΠΆΠ°ΡΡΠ°Ρ ΠΏΠ»ΠΎΡΠ½ΠΎΡΡΠΈ ΡΠ°ΡΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ ΡΠ΅Π·ΡΠ»ΡΡΠΈΡΡΡΡΠ΅Π³ΠΎ ΡΡΠΌΠ° ΠΏΡΠΈ Π±ΠΎΠ»ΡΡΠΎΠΌ ΡΠΈΡΠ»Π΅ ΡΠΈΠΊΠ»ΠΎΠ² ΠΏΠ΅ΡΠ΅Π·Π°ΠΏΠΈΡΠΈ. ΠΠ»Ρ ΡΡΠΎΠΉ ΠΌΠΎΠ΄Π΅Π»ΠΈ ΠΏΡΠΎΠ²ΠΎΠ΄ΠΈΡΡΡ Π°Π½Π°Π»ΠΈΠ· ΠΏΠΎΠΌΠ΅Ρ
ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΠΎΡΡΠΈ ΠΊΠ°ΡΠΊΠ°Π΄Π½ΡΡ
ΠΊΠΎΠ΄ΠΎΠ²ΡΡ
ΠΊΠΎΠ½ΡΡΡΡΠΊΡΠΈΠΉ Ρ Π²Π½Π΅ΡΠ½ΠΈΠΌ ΠΊΠΎΠ΄ΠΎΠΌ Π ΠΈΠ΄Π°-Π‘ΠΎΠ»ΠΎΠΌΠΎΠ½Π° ΠΈ Π²Π½ΡΡΡΠ΅Π½Π½ΠΈΠΌ ΠΌΠ½ΠΎΠ³ΠΎΡΡΠΎΠ²Π½Π΅Π²ΡΠΌ ΠΊΠΎΠ΄ΠΎΠΌ, ΡΠΎΡΡΠΎΡΡΠΈΠΌ ΠΈΠ· Π΄Π²ΠΎΠΈΡΠ½ΡΡ
ΠΊΠΎΠΌΠΏΠΎΠ½Π΅Π½ΡΠ½ΡΡ
ΠΊΠΎΠ΄ΠΎΠ². ΠΡΠΏΠΎΠ»Π½Π΅Π½Π½ΡΠΉ Π°Π½Π°Π»ΠΈΠ· ΠΏΠΎΠ·Π²ΠΎΠ»ΡΠ΅Ρ ΠΏΠΎΠ»ΡΡΠΈΡΡ ΠΎΠ±ΠΌΠ΅Π½Π½ΡΠ΅ ΡΠΎΠΎΡΠ½ΠΎΡΠ΅Π½ΠΈΡ ΠΌΠ΅ΠΆΠ΄Ρ Π²Π΅ΡΠΎΡΡΠ½ΠΎΡΡΡΡ ΠΎΡΠΈΠ±ΠΊΠΈ, ΠΏΠ»ΠΎΡΠ½ΠΎΡΡΡΡ Π·Π°ΠΏΠΈΡΠΈ ΠΈ ΡΠΈΡΠ»ΠΎΠΌ ΡΠΈΠΊΠ»ΠΎΠ² ΠΏΠ΅ΡΠ΅Π·Π°ΠΏΠΈΡΠΈ. ΠΠΎΠ»ΡΡΠ΅Π½Π½ΡΠ΅ ΠΎΠ±ΠΌΠ΅Π½Π½ΡΠ΅ ΡΠΎΠΎΡΠ½ΠΎΡΠ΅Π½ΠΈΡ ΠΏΠΎΠΊΠ°Π·ΡΠ²Π°ΡΡ, ΡΡΠΎ ΠΏΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½Π½ΡΠ΅ ΠΊΠΎΠ½ΡΡΡΡΠΊΡΠΈΠΈ ΠΏΠΎΠ·Π²ΠΎΠ»ΡΡΡ Π·Π° ΡΡΠ΅Ρ ΠΎΡΠ΅Π½Ρ Π½Π΅Π·Π½Π°ΡΠΈΡΠ΅Π»ΡΠ½ΠΎΠ³ΠΎ ΡΠ½ΠΈΠΆΠ΅Π½ΠΈΡ ΠΏΠ»ΠΎΡΠ½ΠΎΡΡΠΈ Π·Π°ΠΏΠΈΡΠΈ ΠΎΠ±Π΅ΡΠΏΠ΅ΡΠΈΡΡ ΡΠ²Π΅Π»ΠΈΡΠ΅Π½ΠΈΠ΅ Π³ΡΠ°Π½ΠΈΡΠ½ΠΎΠ³ΠΎ Π·Π½Π°ΡΠ΅Π½ΠΈΡ ΡΠΈΡΠ»Π° ΡΠΈΠΊΠ»ΠΎΠ² ΠΏΠ΅ΡΠ΅Π·Π°ΠΏΠΈΡΠΈ (ΠΎΠΏΡΠ΅Π΄Π΅Π»ΡΠ΅ΠΌΠΎΠ³ΠΎ ΠΏΡΠΎΠΈΠ·Π²ΠΎΠ΄ΠΈΡΠ΅Π»Π΅ΠΌ) Π² 2β2.5 ΡΠ°Π·Π° ΠΏΡΠΈ ΡΠΎΡ
ΡΠ°Π½Π΅Π½ΠΈΠΈ ΡΡΠ΅Π±ΡΠ΅ΠΌΠΎΠ³ΠΎ Π·Π½Π°ΡΠ΅Π½ΠΈΡ Π²Π΅ΡΠΎΡΡΠ½ΠΎΡΡΠΈ ΠΎΡΠΈΠ±ΠΊΠΈ Π½Π° Π±ΠΈΡ
ΠΠ°ΡΠΊΠ°Π΄Π½ΠΎΠ΅ ΠΊΠΎΠ΄ΠΈΡΠΎΠ²Π°Π½ΠΈΠ΅ Π½Π° ΠΎΡΠ½ΠΎΠ²Π΅ ΠΌΠ½ΠΎΠ³ΠΎΠΌΠ΅ΡΠ½ΡΡ ΡΠ΅ΡΠ΅ΡΠΎΠΊ ΠΈ ΠΊΠΎΠ΄ΠΎΠ² Π ΠΈΠ΄Π° β Π‘ΠΎΠ»ΠΎΠΌΠΎΠ½Π° Π΄Π»Ρ ΠΌΠ½ΠΎΠ³ΠΎΡΡΠΎΠ²Π½Π΅Π²ΠΎΠΉ ΡΠ»ΡΡ-ΠΏΠ°ΠΌΡΡΠΈ
The article considers concatenated coding scheme for multilevel flash memory. In this scheme the inner stage is a finite subset of a multidimensional lattice (lattice code) and the outer stage uses ReedβSolomon code.
Performance analysis is done for a model characterizing the basic physical features of a flash memory cell with non-uniform target voltage levels and noise variance dependent on the recorded value (input-dependent additive Gaussian noise, ID-AGN). For this model we develop a new approach to evaluating the error probability for the inner code. This approach is based on one-dimensional numerical integration of product of the characteristic functions of random variables used in the decoding process. It is shown how the parameters of the concatenated coding scheme can be adapted to keep the required error probability when the retention period and/or number of program-erasure cycles increase.Π ΡΠ°Π±ΠΎΡΠ΅ ΡΠ°ΡΡΠΌΠΎΡΡΠ΅Π½Π° ΠΊΠ°ΡΠΊΠ°Π΄Π½Π°Ρ ΡΡ
Π΅ΠΌΠ° ΠΊΠΎΠ΄ΠΈΡΠΎΠ²Π°Π½ΠΈΡ Π΄Π»Ρ ΠΌΠ½ΠΎΠ³ΠΎΡΡΠΎΠ²Π½Π΅Π²ΠΎΠΉ ΡΠ»ΡΡ-ΠΏΠ°ΠΌΡΡΠΈ, Π²Π½ΡΡΡΠ΅Π½Π½ΡΡ ΡΡΡΠΏΠ΅Π½Ρ ΠΊΠΎΡΠΎΡΠΎΠΉ ΠΏΡΠ΅Π΄ΡΡΠ°Π²Π»ΡΠ΅Ρ ΡΠΎΠ±ΠΎΠΉ ΠΊΠΎΠ½Π΅ΡΠ½ΠΎΠ΅ ΠΏΠΎΠ΄ΠΌΠ½ΠΎΠΆΠ΅ΡΡΠ²ΠΎ ΠΌΠ½ΠΎΠ³ΠΎΠΌΠ΅ΡΠ½ΠΎΠΉ ΡΠ΅Π»ΠΎΡΠΈΡΠ»Π΅Π½Π½ΠΎΠΉ ΡΠ΅ΡΠ΅ΡΠΊΠΈ (lattice code), Π° Π² ΠΊΠ°ΡΠ΅ΡΡΠ²Π΅ Π²Π½Π΅ΡΠ½Π΅ΠΉ ΡΡΡΠΏΠ΅Π½ΠΈ ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΠ΅ΡΡΡ ΠΊΠΎΠ΄ Π ΠΈΠ΄Π° β Π‘ΠΎΠ»ΠΎΠΌΠΎΠ½Π°.
ΠΠ½Π°Π»ΠΈΠ· ΠΏΠΎΠΌΠ΅Ρ
ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΠΎΡΡΠΈ ΠΏΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½Π½ΠΎΠΉ ΠΊΠ°ΡΠΊΠ°Π΄Π½ΠΎΠΉ ΡΡ
Π΅ΠΌΡ Π²ΡΠΏΠΎΠ»Π½Π΅Π½ ΠΏΡΠΈΠΌΠ΅Π½ΠΈΡΠ΅Π»ΡΠ½ΠΎ ΠΊ ΠΌΠΎΠ΄Π΅Π»ΠΈ, ΠΎΡΡΠ°ΠΆΠ°ΡΡΠ΅ΠΉ ΠΎΡΠ½ΠΎΠ²Π½ΡΠ΅ ΡΠΈΠ·ΠΈΡΠ΅ΡΠΊΠΈΠ΅ ΠΎΡΠΎΠ±Π΅Π½Π½ΠΎΡΡΠΈ ΡΡΠ΅ΠΉΠΊΠΈ ΡΠ»ΡΡ-ΠΏΠ°ΠΌΡΡΠΈ Ρ Π½Π΅ΡΠ°Π²Π½ΠΎΠΌΠ΅ΡΠ½ΠΎ ΡΠ°ΡΠΏΠΎΠ»ΠΎΠΆΠ΅Π½Π½ΡΠΌΠΈ ΡΠ΅Π»Π΅Π²ΡΠΌΠΈ ΡΡΠΎΠ²Π½ΡΠΌΠΈ Π½Π°ΠΏΡΡΠΆΠ΅Π½ΠΈΡ Π² ΡΡΠ΅ΠΉΠΊΠ΅ ΠΈ Π΄ΠΈΡΠΏΠ΅ΡΡΠΈΠ΅ΠΉ ΡΡΠΌΠ°, Π·Π°Π²ΠΈΡΡΡΠ΅ΠΉ ΠΎΡ Π·Π°ΠΏΠΈΡΠ°Π½Π½ΠΎΠ³ΠΎ Π·Π½Π°ΡΠ΅Π½ΠΈΡ (input-dependent additive Gaussian noise, ID-AGN). ΠΠ»Ρ ΡΡΠΎΠΉ ΠΌΠΎΠ΄Π΅Π»ΠΈ Π² ΡΠ°Π±ΠΎΡΠ΅ ΡΠ°Π·Π²ΠΈΡ Π½ΠΎΠ²ΡΠΉ ΠΏΠΎΠ΄Ρ
ΠΎΠ΄ ΠΊ Π²ΡΡΠΈΡΠ»Π΅Π½ΠΈΡ Π²Π΅ΡΠΎΡΡΠ½ΠΎΡΡΠΈ ΠΎΡΠΈΠ±ΠΊΠΈ Π΄Π΅ΠΊΠΎΠ΄ΠΈΡΠΎΠ²Π°Π½ΠΈΡ Π²Π½ΡΡΡΠ΅Π½Π½Π΅Π³ΠΎ ΠΊΠΎΠ΄Π° Π½Π° ΠΎΡΠ½ΠΎΠ²Π΅ ΠΎΠ΄Π½ΠΎΠΌΠ΅ΡΠ½ΠΎΠ³ΠΎ ΡΠΈΡΠ»Π΅Π½Π½ΠΎΠ³ΠΎ ΠΈΠ½ΡΠ΅Π³ΡΠΈΡΠΎΠ²Π°Π½ΠΈΡ ΠΏΡΠΎΠΈΠ·Π²Π΅Π΄Π΅Π½ΠΈΠΉ Ρ
Π°ΡΠ°ΠΊΡΠ΅ΡΠΈΡΡΠΈΡΠ΅ΡΠΊΠΈΡ
ΡΡΠ½ΠΊΡΠΈΠΉ ΡΠ»ΡΡΠ°ΠΉΠ½ΡΡ
Π²Π΅Π»ΠΈΡΠΈΠ½, ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΠ΅ΠΌΡΡ
Π΄Π΅ΠΊΠΎΠ΄Π΅ΡΠΎΠΌ ΠΏΡΠΈ Π²ΡΠ½Π΅ΡΠ΅Π½ΠΈΠΈ ΡΠ΅ΡΠ΅Π½ΠΈΡ. ΠΠΎΠΊΠ°Π·Π°Π½ΠΎ, ΠΊΠ°ΠΊ ΠΏΡΠΈ ΡΠ²Π΅Π»ΠΈΡΠ΅Π½ΠΈΠΈ Π²ΡΠ΅ΠΌΠ΅Π½ΠΈ Ρ
ΡΠ°Π½Π΅Π½ΠΈΡ ΠΈ/ΠΈΠ»ΠΈ ΡΠΈΡΠ»Π° ΡΠΈΠΊΠ»ΠΎΠ² ΠΏΠ΅ΡΠ΅Π·Π°ΠΏΠΈΡΠΈ Π°Π΄Π°ΠΏΡΠΈΡΠΎΠ²Π°ΡΡ ΠΏΠ°ΡΠ°ΠΌΠ΅ΡΡΡ ΠΏΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½Π½ΠΎΠΉ ΠΊΠ°ΡΠΊΠ°Π΄Π½ΠΎΠΉ ΠΊΠΎΠ½ΡΡΡΡΠΊΡΠΈΠΈ Ρ ΡΠ΅ΠΌ, ΡΡΠΎΠ±Ρ ΡΠΎΡ
ΡΠ°Π½ΠΈΡΡ ΡΡΠ΅Π±ΡΠ΅ΠΌΡΠΉ ΡΡΠΎΠ²Π΅Π½Ρ Π²Π΅ΡΠΎΡΡΠ½ΠΎΡΡΠΈ ΠΎΡΠΈΠ±ΠΊΠΈ
Improving Reliability and Performance of NAND Flash Based Storage System
High seek and rotation overhead of magnetic hard disk drive (HDD) motivates development of storage devices, which can offer good random performance. As an alternative technology, NAND flash memory demonstrates low power consumption, microsecond-order access latency and good scalability. Thanks to these advantages, NAND flash based solid state disks (SSD) show many promising applications in enterprise servers. With multi-level cell (MLC) technique, the per-bit fabrication cost is reduced and low production cost enables NAND flash memory to extend its application to the consumer electronics.
Despite these advantages, limited memory endurance, long data protection latency and write amplification continue to be the major challenges in the designs of NAND flash storage systems. The limited memory endurance and long data protection latency issue derive from memory bit errors. High bit error rate (BER) severely impairs data integrity and reduces memory durance. The limited endurance is a major obstacle to apply NAND flash memory to the application with high reliability requirement. To protect data integrity, hard-decision error correction codes (ECC) such as Bose-Chaudhuri-Hocquenghem (BCH) are employed. However, the hardware cost becomes prohibitively with the increase of BER when the BCH ECC is employed to extend system lifetime. To extend system lifespan without high hardware cost, we has proposed data pattern aware (DPA) error prevention system design. DPA realizes BER reduction by minimizing the occurrence of data patterns vulnerable to high BER with simple linear feedback shift register circuits. Experimental results show that DPA can increase the system lifetime by up to 4Γ with marginal hardware cost.
With the technology node scaling down to 2Xnm, BER increases up to 0.01. Hard-decision ECCs and DPA are no longer applicable to guarantee data integrity due to either prohibitively high hardware cost or high storage overhead. Soft-decision ECC, such as lowdensity parity check (LDPC) code, has been introduced to provide more powerful error correction capability. However, LDPC code demands extra memory sensing operations, directly leading to long read latency. To reduce LDPC code induced read latency without adverse impact on system reliability, we has proposed FlexLevel NAND flash storage system design. The FlexLevel design reduces BER by broadening the noise margin via threshold voltage (Vth) level reduction. Under relatively low BER, no extra sensing level is required and therefore read performance can be improved. To balance Vth level reduction induced capacity loss and the read speedup, the FlexLevel design identifies the data with high LDPC overhead and only performs Vth reduction to these data. Experimental results show that compared with the best existing works, the proposed design achieves up to 11% read speedup with negligible capacity loss.
Write amplification is a major cause to performance and endurance degradation of the NAND flash based storage system. In the object-based NAND flash device (ONFD), write amplification partially results from onode partial update and cascading update. Onode partial update only over-writes partial data of a NAND flash page and incurs unnecessary data migration of the un-updated data. Cascading update is update to object metadata in a cascading manner due to object data update or migration. Even through only several bytes in the object metadata are updated, one or more page has to be re-written, significantly degrading write performance. To minimize write operations incurred by onode partial update and cascading update, we has proposed a Data Migration Minimizing (DMM) device design. The DMM device incorporates 1) the multi-level garbage collection technique to minimize the unnecessary data migration of onode partial update and 2) the virtual B+ tree and diff cache to reduce the write operations incurred by cascading update. The experiment results demonstrate that the DMM device can offer up to 20% write reduction compared with the best state-of-art works