Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness

In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation experiments, we investigate the impact of the rms amplitude /spl Delta/ and the correlation length /spl Lambda/ on the intrinsic parameter fluctuations in well scaled, but simple devices with fixed geometry as well as the channel length and width dependence of the fluctuations at fixed LER parameters. For the first time, we superimpose in the simulations LER and random discrete dopants and investigate their relative contribution to the intrinsic parameter fluctuations in the investigated devices. For particular MOSFET geometries, we were able to identify the regions where each of these two sources of intrinsic parameter fluctuations dominates

Gate oxide failure in MOS devices

The thesis presents an experimental and theoretical investigation of gate oxide breakdown in MOS networks, with a particular emphasis on constant voltage overstress failure. It begins with a literature search on gate oxide failure mechanisms, particularly time-dependent dielectric breakdown, in MOS devices. The experimental procedure is then reported for the study of gate oxide breakdown under constant voltage stress. The experiments were carried out on MOSFETs and MOS capacitor structures, recording the characteristics of the devices before and after the stress. The effects of gate oxide breakdown in one of the transistors in an nMOS inverter were investigated and several parameters were found to have changed. A mathematical model for oxide breakdown, based on physical mechanisms, is proposed. Both electron and hole trapping occurred during the constant voltage stress. Breakdown appears to take place when the trapped hole density reach a critical value. PSPICE simulations were performed for the MOSFETs, nMOS inverter and CMOS logic circuits. Two models of MOSFET with gate oxide short were validated. A good agreement between experiments and simulations was achieved

Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation

This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated

A Study on SPICE Modeling of Non-Resonant Plasmonic Terahertz Detector

Department Of Electrical EngineeringThe terahertz (sub-millimeter wave) is the frequency resource, ranging from 100 GHz ~ 10 THz band, located in the middle region of the infrared and millimeter waves in the electromagnetic spectrum. Terahertz waves has unique physical characteristics, which is transparency of radio waves and straightness of light waves, simultaneously. The terahertz wave is applied to the basic science, such as device, spectroscopy, and imaging technology. And also adjust in the applied science, such as biomedical engineering, security, environment, information and communication. Which importance already verified. In the new shape of future market is expected to be formed broadly. For this application, operating in the THz frequency detecting device essential. Recently, Current elements operating in terahertz are present, such as compound semiconductor (???-???HBT, HEMT). But, there are disadvantage to use as a high price. Therefore, research have been made of silicon based THz detector in many research groups. Silicon-based nano-technology utilizes a plasma wave transistor technology. Which is using the space-time change of the channel charge density. That causes plasma wave oscillation in the MOSFET (Metal oxide semiconductor field effect transistor) channel and this effect available MOSET operating terahertz regime beyond MOSFET cut-off frequency. So, PWT (plasma wave transistor) is available terahertz detection and oscillation. For integrated possible post processing circuit development in these of terahertz applications system, silicon based PWT compact model is essential thing. For this compact model for spice simulation beyond cut-off frequency, we consider charge time variance model which is NQS (non-quasi-static) model, not quasi-static model. For NQS model two kinds of model exist, first is RC ladder model. That is seral connect MOSFET get rid of parasitic elements. And these complex circuit making the equivalent circuit model, it called New Elmore model. For post processing circuit simulation, fast simulation speed is essential, RC ladder model has a disadvantage (for simulating each segment). In this thesis we using New Elmore model based on Non-resonant plasmonic THz detector modeling, And verified physical validity of our NQS model using the our TCAD model based on Quasi-plasma 2DEG. And we propose fast and accurate compact modelingope