Computer Aided Design of MIC layouts with Postprocessor for Photoplotter

A PC-based computer-aided design (CAD) package for designing microwave integrated circuit (MIC) printed circuit board (PCB) layout, called microwave artwork postprocessor for photoplotter (MAPP), is developed. The small size of MIC PCBs makes them suitable for defence applications. MAPP has a postprocessor which converts the MIC layout data to a format acceptable as input to a Gerber photoplotter. Photomask of the PCB is obtained from the photoplotter. This paper presents the methodology for the CAD of MIC layouts and also discusses the algorithm for filling of a general polygon with curved edges, and which lies in the real domain. This algorithm is used in the postprocessor for a photoplotter

The large scale microelectronics Computer-Aided Design and Test (CADAT) system

The CADAT system consists of a number of computer programs written in FORTRAN that provide the capability to simulate, lay out, analyze, and create the artwork for large scale microelectronics. The function of each software component of the system is described with references to specific documentation for each software component

Applications of dynamic programming tp problems of routing pipework and cables

Imperial Users onl

Printed circuit board design in a school computer laboratory

Printed Circuit Boards replaced conventional wiring in most electronic equipment after World War II, reducing the size and weight of equipment while improving reliability and uniformity. PCBs are used in all kinds of electrical and electronic products because they can be mass-produced with greater circuit density and also enable easier trouble-shooting. Computer Aided Design (CAD) is critical in teaching PCB layout design but it is a challenge for school and college instructors with limited budgets. After discussion of current trends in PCB design and development, as well as basic PCB design criteria, an affordable PCB design using an " educational" microcomputer is presented

Computer aids for the design of large scale integrated circuits.

The work described in this thesis is concerned with the development of CADIC (Computer Aided Design of Integrated Circuits), a suite of computer programs which allows the user to design integrated circuit layouts at the geometric level. Initially, a review of existing computer aids to integrated circuit design is carried out. Advantages and disadvantages of each computer aid is discused, and the approach taken by CADIC justified in the light of the review. The hardware associated with a design aid can greatly influence its performance and useability. For this reason, a critical review of available graphic terminals is also undertaken. The requirements, logistics, and operation of CADIC is then discussed in detail. CADIC provides a consise range of features to aid in the design and testing of integrated circuit layouts. The most important features are however CADIC's high efficiency in processing layout data, and the implementation of complete on-line design rule checking. Utilization of these features allows CADIC to substantially reduce the lengthy design turnaround time normally associated with manual design aids. Finally, the performance of CADIC is presented. Analysis of the results show that CADIC is very efficient at data processing, especially when small sections of the layout are considered. CADIC can also perform complete on-line design rule checking well within the time it takes the designer to start adding the next shape

Computer aided design of printed wiring boards

A method is described for the computer-aided layout of printed wiring boards. The type of board considered is a single sided board containing discrete components. The required input for the layout algorithm is coded from the relevant circuit diagram, together with a description of the component dimensions. This information is then stored within the computer in a data structure. The circuit components and their interconnections are represented by a set of nodes and branches. The principles of graph theory are used to construct an abstract model of the layout. A number of the nodes and branches of the circuit are first used in the construction of a planar graph. A method is then described for inserting the remaining branches into the graph to form a "pseudo planar graph". This represents a set of components and conductor paths which can be laid out on a single sided board without intersections. The number of conductor crossings is thus minimised before the actual layout commences. An algorithm is then described for automatically constructing a board layout from the pseudo planar graph. The relative interconnections are already known so the placement of components and routing of conductor paths can proceed simultaneously. The layout is therefore constructed in a series of logical steps working across from one edge of the board to the other. This approach contrasts with the more usual methods of layout in which components are placed first, followed by a search for conductor routes. The layout algorithm is also provided with facilities for man-machine interaction by means of a graphical display and light pen. Interaction allows the user to alter the positions of components during the construction of the layout. Thus the skill and experience of the user can be combined with the speed and accuracy of the automatic algorithm. Interaction also enables special conditions to be incorporated into the layout which would otherwise entail considerable programming effort. Three different circuits are used to test the layout algorithm. The results are shown for layouts constructed both automatically and by the use of interaction. One layout is also compared with a manually-produced layout of the same circuit. The results show that a feasible method has been developed for the layout of printed wiring boards by computer. Comparable results are produced in considerably less time than normal layout methods