TOPOLOGY, ANALYSIS, AND CMOS IMPLEMENTATION OF SWITCHED-CAPACITOR DC-DC CONVERTERS

This review highlights various design and realization aspects of three commonly used charge pump topologies, namely, the linear, exponential, and the Fibonacci type of charge pumps. We shall outline the new methods developed recently for analyzing the steady and dynamic performances of these circuits. Some practical issues for the CMOS implementation of these charge pump structures will be critically discussed. Finally, some conventional voltage regulation methods for maintaining a stable output under a large range of loading current and supply voltage fluctuations will be proposed

Design Space Evaluation for Resonant and Hard-charged Switched Capacitor Converters

USB Power Delivery enables a fixed ratio converter to operate over a wider range of output voltages by varying the input voltage. Of the DC/DC step-down converters powered from this type of USB, the hard-charged Switched Capacitor circuit is of interest to industry for its potential high power density. However implementation can be limited by circuit efficiency. In fully resonant mode, the efficiency can be improved while also enabling current regulation. This expands the possible applications into battery chargers and eliminates the need for a two-stage converter.In this work, the trade-off in power loss and area between the hard-charged and fully resonant switched capacitor circuit is explored using a technique that remains agnostic to inductor technology. The loss model for each converter is presented as well as discussion on the restrained design space due to parasitics in the passive components. The results are validated experimentally using GaN-based prototype converters and the respective design spaces are analyzed

Hard-switched switched capacitor converter design

Switched capacitor (SC) converters are becoming quite popular for use in DC-DC power conversion. The concept of equivalent resistance in SC converters is frequently used to determine the conduction losses due to the load current. A variety of methodologies have been presented in the literature to predict the equivalent resistance in hard-switched SC converters. However, a majority of the methods described are difficult to apply to general SC converter topologies. Additionally, previous works have not considered all nonidealities in their analysis, such as switching losses or stray inductances. This work presents a generalized and easy to use model to determine the equivalent resistance of any high-order SC converter. The presented concepts are combined to derive a complete loss model for SC converters. The challenges of implementing output voltage regulation are addressed as well. A current-fed SC topology is presented in this work that overcomes the problems associated with voltage regulation. The new topology opens up a variety of additional operating modes, such as power sharing. These additional operating modes are explored as well. The presented concepts are verified using digital simulation tools and prototype converters. --Abstract, page iii

Low Power Switched Capacitor DC-DC Converters for Low Power Transceiver Applications

DC-DC converters, also known as switching voltage regulators, are one of the main components of a power management unit. Their main role is to provide a constant, smooth output voltage to power the electronic devices. Recent miniaturi-zation trend of electronics circuitry has led to the need for smaller and high-efficient DC-DC converters in current and future applications. This thesis presents a Switched Capacitor (SC) based DC-DC converter, which can directly operate at input voltage of 4.2V on 45nm CMOS process. Currently, most of the DC-DC converters on 45nm are not able to operate at such high volt-ages. Moreover, SC architecture has resulted in smaller size of converter com-pared with LC type DC-DC converters. The design uses three SC topologies, which include two novel SC topologies of 2/5 and 2/7. Devices break down conditions have been overcome by implement-ing some of the MOS switches in cascoded structures. The converter structure uses eight phase interleaving approach to reduce output ripple to as low as 25mV level. In addition to the main SC structure, a four-stage differential ring oscillator is de-signed for providing quadrature clock signals to the SC topologies. Clock genera-tor can be enabled/disabled from outside the chip, through an enable (EN) pin. For instance, the EN pin can be used for regulating the output voltage in Pulse Fre-quency Modulation (PFM) feedback approach. /Kir1

Analysis and design of switched-capacitor DC-DC converters with discrete event models

Ph. D. Thesis.Switched-capacitor DC-DC converters (SCDDCs) play a critical role in low power integrated systems. The analysis and design processes of an SCDDC impact the performance and power efficiency of the whole system. Conventionally, researchers carry out the analysis and design processes by viewing SCDDCs as analogue circuits. Analogue attributes of an SCDDC, such as the charge flow current or the equivalent output impedance, have been studied in considerable detail for performance enhancement. However, in most existing work, less attention is paid to the analysis of discrete events (e.g. digital signal transitions) and the relationships between discrete events in SCDDCs. These discrete events and the relationships between discrete events also affect the performance of SCDDCs. Certain negative effects of SCDDCs such as leakage current are introduced by unhealthy discrete states. For example, MOS devices in an SCDDC could conduct undesirably under certain combinations of signals, resulting in reversion losses (a type of leakage in SCDDCs). However, existing work only use verbal reasoning and waveform descriptions when studying these discrete events, which may cause confusion and result in an informal design process consisting of intuitive design and backed up merely by validation based on natural language discussions and simulations. There is therefore a need for formalised methods to describe and analyse these discrete events which may facilitate systematic design techniques. This thesis presents a new method of analysing and designing SCDDCs using discrete event models. Discrete event models such as Petri nets and Signal Transition Graphs (STGs) are commonly used in asynchronous circuits to formally describe and analyse the relationships between discrete transitions. Modelling SCDDCs with discrete event models provides a formal way to describe the relations between discrete transitions in SCDDCs. These discrete event models can be used for analysis, verification and even design guidance for SCDDC design. The rich set of existing analysis methods and tools for discrete event models could be applied to SCDDCs, potentially improving the analysis and design flow for them. Moreover, since Petri nets and STGs are generally used to analyse and design asynchronous circuits, modelling and designing SCDDCs with STG models may additionally facilitate the incorporation of positive features of asynchronous circuits in SCDDCs (e.g. no clock skew). In this thesis, the relations between discrete events in SCDDCs are formally described with SC-STG (an extended STG targeting multi-voltage systems, to which SCDDCs belong), which avoids the potential confusion due to natural language and waveform descriptions. Then the concurrency and causality relations described in SC-STG model are extended to Petri nets, with which the presence of reversion losses can be formally determined and verified. Finally, based on the STG and Petri net models, a new design method for reversion-loss-free SCDDCs is proposed. In SCDDCs designed with the new method, reversion losses are entirely removed by introducing asynchronous controls, synthesised with the help of a software synthesis toolkit “Workcraft”. To demonstrate the analysis capabilities of the method, several cross-coupled voltage doublers (a type of SCDDC) are analysed and studied with discrete event models as examples in this thesis. To demonstrate the design capabilities of the method, a new reversion-loss-free cross-coupled voltage doubler is designed. The cross-coupled voltage doubler is widely used in low power integrated systems such as flash memories, LCD drivers and wireless energy harvesting systems. The proposed modelling method is potentially used in both research and industrial area of those applications for a formal and high-efficiency design proces

Industrial and Technological Applications of Power Electronics Systems

The Special Issue "Industrial and Technological Applications of Power Electronics Systems" focuses on: - new strategies of control for electric machines, including sensorless control and fault diagnosis; - existing and emerging industrial applications of GaN and SiC-based converters; - modern methods for electromagnetic compatibility. The book covers topics such as control systems, fault diagnosis, converters, inverters, and electromagnetic interference in power electronics systems. The Special Issue includes 19 scientific papers by industry experts and worldwide professors in the area of electrical engineering

Advanced control system for stand-alone diesel engine driven-permanent magnetic generator sets

The main focus is on the development of an advanced control system for variable speed standalone diesel engine driven generator systems. An extensive literature survey reviews the historical development and previous relevant research work in the fields of diesel engines, electrical machines, power electronic converters, power and electronic systems. Models are developed for each subsystem from mathematical derivations with necessary simplifications made to reduce complexity while retaining the required accuracy. Initially system performance is investigated using simulation models in Matlab/Simulink. The AC/DC/AC power electronic conversion system used employs a voltage controlled dc link. The ac voltage is maintained at constant magnitude and frequency by using a dc-dc converter and a fixed modulation ratio VSI PWM inverter. The DC chopper provides fast control of the output voltage by dealing efficiently with transient conditions. A Variable Speed Fuzzy Logic Core (VSFLC) controller is combined with a classical control method to produce a novel hybrid controller. This provides an innovative variable speed control that responds to both load and speed changes. A new power balance based control strategy is proposed and implemented in the speed controller. Subsequently a novel overall control strategy is proposed to co-ordinate the hybrid variable speed controller and chopper controller to provide overall control for both fast and slow variations of system operating conditions. The control system is developed and implemented in hardware using Xilinx Foundation Express. The VHDL code for the complete control system design is developed and the designs are synthesised and analysed within the Xilinx environment. The controllers are implemented with XC95108-PC84 and XC4010-PC84 to provide a compact and cheap control system. A prototype experimental system is described and test results are obtained that show the combined control strategy to be very effective. The research work makes contributions in the areas of automatic control systems for diesel engine generator sets and CPLD/FPGA application that will benefit manufacturers and consumers.EPSR

Electronics for Sensors

The aim of this Special Issue is to explore new advanced solutions in electronic systems and interfaces to be employed in sensors, describing best practices, implementations, and applications. The selected papers in particular concern photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs) interfaces and applications, techniques for monitoring radiation levels, electronics for biomedical applications, design and applications of time-to-digital converters, interfaces for image sensors, and general-purpose theory and topologies for electronic interfaces

Development of an autonomous lab-on-a-chip system with ion separation and conductivity detection for river water quality monitoring

This thesis discusses the development of a lab on a chip (LOC) ion separation for river water quality monitoring using a capacitively coupled conductivity detector (C⁴D) with a novel baseline suppression technique.Our first interest was to be able to integrate such a detector in a LOC. Different designs (On-capillary design and on-chip design) have been evaluated for their feasibility and their performances. The most suitable design integrated the electrode close to the channel for an enhanced coupling while having the measurement electronics as close as possible to reduce noise. The final chip design used copper tracks from a printed circuit board (PCB) as electrodes, covered by a thin Polydimethylsiloxane (PDMS) layer to act as electrical insulation. The layer containing the channel was made using casting and bonded to the PCB using oxygen plasma. Flow experiments have been conduced to test this design as a detection cell for capacitively coupled contactless conductivity detection (C⁴D).The baseline signal from the system was reduced using a novel baseline suppression technique. Decrease in the background signal increased the dynamic range of the concentration to be measured before saturation occurs. The sensitivity of the detection system was also improved when using the baseline suppression technique. Use of high excitation voltages has proven to increase the sensitivity leading to an estimated limit of detection of 0.0715 μM for NaCl (0.0041 mg/L).The project also required the production of an autonomous system capable of operating for an extensive period of time without human intervention. Designing such a system involved the investigation of faults which can occur in autonomous system for the in-situ monitoring of water quality. Identification of possible faults (Bubble, pump failure, etc.) and detection methods have been investigated. In-depth details are given on the software and hardware architecture constituting this autonomous system and its controlling software