Sonar ultrassónico para cegos com sonificação de obstáculos

In this master’s thesis it is intended to develop a portable device that can be used by people with visual impairment in the echolocation of obstacles. This device must be capable of transmitting and detecting ultrasound signals to work as a sonar and still allow its operation as a parametric speaker capable of performing the sonification of obstacles. To do this, it was necessary to develop a Sigma-Delta ADC in FPGA that allows a high density in the independent acquisition of a large number of channels in a small device. Tests performed with the developed Sigma-Delta ADC revealed low distortion and good signal-to-noise ratio, comparable to same type ADCs available on the market. The path for the construction of the device is, then, open.Nesta tese de mestrado pretende-se desenvolver um dispositivo portátil que possa ser usado por pessoas com deficiência visual na ecolocalização de obstáculos. Este dispositivo deverá ser dotado de capacidade de emissão e deteção de ultrassons para funcionar como um sonar e permitir ainda o seu funcionamento como altifalante paramétrico capaz de realizar a sonificação dos obstáculos. Para tal, foi necessário desenvolver uma ADC Sigma-Delta em FPGA que permita uma alta densidade na aquisição independente de um grande número de canais num dispositivo de pequenas dimensões. Os testes realizados com a ADC Sigma-Delta revelaram uma baixa distorção e uma boa relação sinal ruı́do, comparáveis às ADCs do mesmo tipo existentes no mercado. Está assim preparado o caminho para a construção do dispositivo.Mestrado em Engenharia Eletrónica e Telecomunicaçõe

Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator

The demand for higher data rates in receivers with carrier aggregation (CA) such as LTE, increases the efforts to integrate large number of wireless services into single receiving path, so it needs to digitize the signal in intermediate or high frequencies. It relaxes most of the front-end blocks but makes the design of ADC very challenging. Solving the bottleneck associated with ADC in receiver architecture is a major focus of many ongoing researches. Recently, continuous time Sigma-Delta analog-to-digital converters (ADCs) are getting more attention due to their inherent filtering properties, lower power consumption and wider input bandwidth. But, it suffers from several non-idealities such as clock jitter and ELD which decrease the ADC performance. This dissertation presents two projects that address CT-ΣΔ modulator non-idealities. One of the projects is a CT- ΣΔ modulator with 10.9 Effective Number of Bits (ENOB) with Gradient Descent (GD) based calibration technique. The GD algorithm is used to extract loop gain transfer function coefficients. A quantization noise reduction technique is then employed to improve the Signal to Quantization Noise Ratio (SQNR) of the modulator using a 7-bit embedded quantizer. An analog fast path feedback topology is proposed which uses an analog differentiator in order to compensate excess loop delay. This approach relaxes the requirements of the amplifier placed in front of the quantizer. The modulator is implemented using a third order loop filter with a feed-forward compensation paths and a 3-bit quantizer in the feedback loop. In order to save power and improve loop linearity a two-stage class-AB amplifier is developed. The prototype modulator is implemented in 0.13μm CMOS technology, which achieves peak Signal to Noise and Distortion Ratio (SNDR) of 67.5dB while consuming total power of 8.5-mW under a 1.2V supply with an over sampling ratio of 10 at 300MHz sampling frequency. The prototype achieves Walden's Figure of Merit (FoM) of 146fJ/step. The second project addresses clock jitter non-ideality in Continuous Time Sigma Delta modulators (CT- ΣΔM), the modulator suffer from performance degradation due to uncertainty in timing of clock at digital-to-analog converter (DAC). This thesis proposes to split the loop filter into two parts, analog and digital part to reduce the sensitivity of feedback DAC to clock jitter. By using the digital first-order filter after the quantizer, the effect of clock jitter is reduced without changing signal transfer function (STF). On the other hand, as one pole of the loop filter is implemented digitally, the power and area are reduced by minimizing active analog elements. Moreover, having more digital blocks in the loop of CT- ΣΔM makes it less sensitive to process, voltage, and temperature variations. We also propose the use of a single DAC with a current divider to implement feedback coefficients instead of two DACs to decrease area and clock routing. The prototype is implemented in TSMC 40 nm technology and occupies 0.06 mm^2 area; the proposed solution consumes 6.9 mW, and operates at 500 MS/s. In a 10 MHz bandwidth, the measured dynamic range (DR), peak signal-to-noise-ratio (SNR), and peak signal-to-noise and distortion (SNDR) ratios in presence of 4.5 ps RMS clock jitter (0.22% clock period) are 75 dB, 68 dB, and 67 dB, respectively. The proposed structure is 10 dB more tolerant to clock jitter when compared to the conventional ΣΔM design for similar loop filter

A survey on continuous-time modulators : theory, designs and implementations

Recently, delta-sigma modulation has become a widely applied technique for high-performance analog-to-digital conversion of narrow-band signals. Most of the early designs used discrete-time structure for good accuracy and good linearity. The transfer functions are independent of the clock frequency. However, high unity-gain bandwidths of the opamps are required to satisfy the settling accuracy required in the discrete-time designs. Continuous-time structure can potentially achieve higher clock frequency with less power consumption. the anti-aliasing filter can also be eliminated due to the anti-aliasing property of CT modulators. On the other hand, CT ADC have their own problems, such as jitter sensitivity and excess loop delay. In this thesis, the state-of-the-art of CT modulator is reviewed. The problems in the design of CT ADCs are analyzed and solutions to them are described. The theory, design and implementations of CT modulator will also be reviewed.Keywords: Continuous-Time, Delta-Sigm

Design of low OSR, high precision analog-to-digital converters

Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures. In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18μm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs.Keywords: Delta-Sigma, Loop Filter, Oversampled ADC, Gain Stage, Pipeline, Noise Shapin

Analysis of Current Conveyor based Switched Capacitor Circuits for Application in ∆Σ Modulators

The reduction in supply voltage, loss of dynamic range and increased noise prevent the analog circuits from taking advantage of advanced technologies. Therefore the trend is to move all signal processing tasks to digital domain where advantages of technology scaling can be used. Due to this, there exists a need for data converters with large signal bandwidths, higher speeds and greater dynamic range to act as an interface between real world analog and digital signals. The Delta Sigma (∆Σ) modulator is a data converter that makes use of large sampling rates and noise shaping techniques to achieve high resolution in the band of interest. The modulator consists of analog integrators and comparators which create a modulated digital bit stream whose average represents the input value. Due to their simplicity, they are popular in narrow band receivers, medical and sensor applications. However Operational Amplifiers (Op-Amps) or Operational Transconductance Amplifiers (OTAs), which are commonly used in data converters, present a bottleneck. Due to low supply voltages, designers rely on folded cascode, multistage cascade and bulk driven topologies for their designs. Although the two stage or multistage cascade topologies offer good gain and bandwidth, they suffer from stability problems due to multiple stages and feedback requiring large compensation capacitors. Therefore other low voltage Switched-Capacitor (SC) circuit techniques were developed to overcome these problems, based on inverters, comparators and unity gain buffers. In this thesis we present an alternative approach to design of ∆Σ modulators using Second Generation Current Conveyors (CCIIs). The important feature of these modulators is the replacement of the traditional Op-Amp based SC integrators with CCII based SC integrators. The main design issues such as the effect of the non-idealities in the CCIIs are considered in the operation of SC circuits and solutions are proposed to cancel them. Design tradeoffs and guidelines for various components of the circuit are presented through analysis of existing and the proposed SC circuits. A two step adaptive calibration technique is presented which uses few additional components to measure the integrator input output characteristic and linearize it for providing optimum performance over a wide range of sampling frequencies while maintaining low power and area. The presented CCII integrator and calibration circuit are used in the design of a 4th order (2-2 cascade) ∆Σ modulator which has been fabricated in UMC 90nm/1V technology through Europractice. Experimental values for Signal to Noise+Distortion Ratio (SNDR), Dynamic Range (DR) and Figure Of Merit (FOM) show that the modulator can compete with state of art reconfigurable Discrete-Time (DT) architectures while using lower gain stages and less design complexity

Novas arquiteturas para transmissores digitais flexíveis e de banda larga

Next generation of wireless communication (5G) devices must achieve higher data rates, lower power consumption and better coverage by making a more efficient use of the RF spectrum and adopting highly exible radio architectures. To meet these requirements, the development of new radio devices will be far more complex and challenging than their predecessors. The future of radio communications have a twofold evolution, being one the low power consumption and the other the adaptability and intelligent use of the available resources. Conventional approaches for the radio physical layer are not capable to cope with the new demand for multi-band, multi-standard radio signals and present an inefficient and expensive solution for simultaneous transmission of multiple and heterogeneous radio signals. Digital radio transmitters have been presented as a solution for a newer and more exible architecture for future radios. All-digital transmitters use a completely digital implementation of the entire radio datapath from the baseband processing to the digital RF up-conversion. This concept bene ts from the use of highly integrated hardware together with a strong radio digitalization, motivated by the exibility and high performance from cognitive and software defi ned radio. However, such devices are still far from a massive deployment in most of communication scenarios due to some limiting factors that hinder their use. This PhD thesis aims to the development of novel radio architectures and ideas based on all-digital transmitters capable of improving the adaptability and use intelligently the available resources for software de ned and cognitive radio systems. The focus of this thesis is on the improvement of some of the common limitations for all-digital transmitters such as power efficiency, bandwidth, noise-shaping and exibility while using efficient and adaptable digital architectures. In the initial part of the thesis a review of the state-of-the-art is presented showing the most common digital transmitter architectures as well as their major bene ts and key limitations. A comparative analysis of such architectures is made considering their power and spectral efficiency, exibility, performance and cost. Following this initial analysis, the work developed on the course of this PhD is presented and discussed. The initial focus is on the improvement of all-digital transmitters bandwidth trough the study and use of parallel processing techniques capable of greatly improve common bandwidth values presented in the state-of-the-art. The presented work has resulted in several publications where FPGA-based architectures use parallel digital processing techniques to improve the system's bandwidth by a factor higher than 10. Other fundamental contribution of this thesis is focused on the pulsedtransmitters coding efficiency. In this section of the thesis, a method is presented showing the reduction of the quantization noise created by low amplitude resolution digital transmitters using multiple combined pulsedtransmitters to cancel the noise in speci c frequencies. This work has resulted in two main publications that showed how to increase the coding efficiency of the pulse-transmitters as well as the overall efficiency of the transmission system. Lastly, new-noise shaping methods are presented in order to develop new and more exible architectures for all-digital transmitters. The methods presented use new quantization processes that allow for the shaping of the quantization noise produced in pulsed-transmitters while using very simple and adaptable architectures. With these new techniques, it is possible to adjust the noise frequency distribution and deliberately change the noise shape in order to change some of the transmitter's characteristics such as central frequency or bandwidth. The work presented on this thesis has shown promising improvements to the all-digital transmitters' state-of-the-art, either in simulations and laboratory prototype measurements. It has contributed to advance the state-of-the-art in agile and power efficient all-digital RF transmitters with multi-mode and multi-channel capabilities and the improvement of the transceiver's bandwidth enabling the development of true software de ned and cognitive radio systemsA próxima geração de comunicações sem os (5G) exigirá taxas de transmissão mais elevadas, maior efi ciência energética e uma melhor cobertura fazendo um uso mais efi ciente do espectro de radiofrequência e adotando o uso de arquiteturas rádio mais flexíveis. Para cumprir tais requisitos, o desenvolvimento de novos dispositivos rádio será substancialmente mais complexo do que nas gerações anteriores. O futuro das comunicações rádio depende maioritariamente de dois fatores; o baixo consumo de potência e o uso inteligente dos recursos e tecnologias disponíveis. As abordagens convencionais para a camada física dos sistemas rádio não são as mais adequadas para lidar com a necessidade de dispositivos multi-banda e que usem múltiplos standards, por serem soluções inefi cientes e demasiado caras para esse efeito. Os transmissores rádio completamente digitais têm vindo a ser apresentados na literatura como uma solução inovadora e mais flexível para a implementação dos futuros sistemas de rádio. Os transmissores completamente digitais apresentam uma implementação da cadeia de processamento rádio, desde a banda-base até à conversão para RF, completamente constituída por lógica digital. Este conceito tira partido da vasta integração alcançada nas arquiteturas digitais, juntamente com a flexibilidade proveniente da digitalização das arquiteturas rádio que já se encontra em curso com a evolução dos rádios cognitivos e definidos por software. No entanto, devido a algumas limitações inerentes à tecnologia, este tipo de transmissores ainda não é amplamente utilizado na maioria dos sistemas. Esta tese de doutoramento propõe e avalia novas arquiteturas para transmissores completamente digitais, bem como novas técnicas de processamento de sinal que possam beneficiar das tecnologias de implementação existentes (e.g. FPGAs) por forma a construir novos transmissores digitais de forma eficiente e flexível. O objetivo desta tese é reduzir as limitações atuais ainda presentes neste tipo de transmissores, nomeadamente as relacionadas com a eficiência, largura de banda, cancelamento de ruído e falta de flexibilidade. Na parte inicial desta tese é realizada a revisão do estado da arte das diversas topologias de transmissores digitais bem como as suas principais vantagens e limitações técnicas. É também feita uma análise comparativa das diversas técnicas apresentadas em termos da sua eficiência energética, flexibilidade, desempenho e custo. De seguida, é apresentado o trabalho desenvolvido no contexto desta tese de doutoramento, seguindo-se uma discussão focada na resolução das atuais limitações deste tipo de transmissores. A primeira parte foca-se no uso de técnicas de processamento paralelo de sinal, por forma a suportar sinais de largura de banda mais elevada que os reportados no atual estado da arte. O trabalho desenvolvido e publicado baseia-se no uso de arquiteturas implementadas em FPGA que contribuíram para um aumento da largura de banda num fator de aproximadamente dez vezes. Outra das contribuições fundamentais desta tese consiste no aumento da eficiência do sistema através da melhoria da eficiência de codificação do sinal pulsado produzido. Com base no uso de múltiplos transmissores pulsados, e apresentado um esquema de combinação construtiva e destrutiva de sinais para a redução do ruído de quantização proveniente das técnicas de processamento de sinal pulsado usadas. Este trabalho resultou em duas importantes publicações que mostram que a melhoria da eficiência de codificação do sinal pode ser utilizada de forma a obter uma maior eficiência energética do transmissor. Por ultimo, são apresentadas diversas técnicas para a conversão dos sinais banda-base em sinais RF pulsados. As propostas apresentadas permitem o uso de uma arquitetura de hardware simplista, mas configurável por software, o que a torna bastante flexível. Com o uso desta arquitetura e possível alterar em pleno funcionamento a frequência central bem como a largura de banda e resposta do conversor pulsado. O trabalho apresentado nesta tese demonstra alguns dos melhoramentos no estado da arte para transmissores r adio completamente digitais, baseando os resultados obtidos não apenas em simulações mas também na implementação e medidas realizadas sobre protótipos laboratoriais. O trabalho desenvolvido no âmbito desta tese contribuiu com avanços na implementação de transmissores ageis, eficientes, com maior largura de banda e capazes de transmissão em múltiplas bandas com recurso a múltiplos protocolos, abrindo caminho para o desenvolvimento de novos rádios cognitivos e definidos por softwareFCT, FSEPrograma Doutoral em Engenharia Eletrotécnic

An implantable micro-system for neural prosthesis control and sensory feedback restoration in amputees

In this work, the prototype of an electronic bi-directional interface between the Peripheral Nervous System (PNS) and a neuro-controlled hand prosthesis is presented. The system is composed of two Integrated Circuits (ICs): a standard CMOS device for neural recording and a High Voltage (HV) CMOS device for neural stimulation. The integrated circuits have been realized in two different 0.35μm CMOS processes available fromAustriaMicroSystem(AMS). The recoding IC incorporates 8 channels each including the analog front-end and the A/D conversion based on a sigma delta architecture. It has a total area of 16.8mm2 and exhibits an overall power consumption of 27.2mW. The neural stimulation IC is able to provide biphasic current pulses to stimulate 8 electrodes independently. A voltage booster generates a 17V voltage supply in order to guarantee the programmed stimulation current even in case of high impedances at the electrode-tissue interface in the order of tens of k­. The stimulation patterns, generated by a 5-bit current DAC, are programmable in terms of amplitude, frequency and pulse width. Due to the huge capacitors of the implemented voltage boosters, the stimulation IC has a wider area of 18.6mm2. In addition, a maximum power consumption of 29mW was measured. Successful in-vivo experiments with rats having a TIME electrode implanted in the sciatic nerve were carried out, showing the capability of recording neural signals in the tens of microvolts, with a global noise of 7μVrms , and to selectively elicit the tibial and plantarmuscles using different active sites of the electrode. In order to get a completely implantable interface, a biocompatible and biostable package was designed. It hosts the developed ICs with the minimal electronics required for their proper operation. The package consists of an alumina tube closed at both extremities by two ceramic caps hermetically sealed on it. Moreover, the two caps serve as substrate for the hermetic feedthroughs to enable the device powering and data exchange with the external digital controller implemented on a Field-Programmable Gate Array (FPGA) board. The package has an outer diameter of 7mm and a total length of 26mm. In addition, a humidity and temperature sensor was also included inside the package to allow future hermeticity and life-time estimation tests. Moreover, a wireless, wearable and non-invasive EEG recording system is proposed in order to improve the control over the artificial limb,by integrating the neural signals recorded from the PNS with those directly acquired from the brain. To first investigate the system requirements, a Component-Off-The-Shelf (COTS) device was designed. It includes a low-power 8- channel acquisition module and a Bluetooth (BT) transceiver to transmit the acquired data to a remote platform. It was designed with the aimof creating a cheap and user-friendly system that can be easily interfaced with the nowadays widely spread smartphones or tablets by means of a mobile-based application. The presented system, validated through in-vivo experiments, allows EEG signals recording at different sample rates and with a maximum bandwidth of 524Hz. It was realized on a 19cm2 custom PCB with a maximum power consumption of 270mW