Complementary Communication Path for Energy Efficient On-Chip Optical Interconnects

International audienceOptical interconnects are considered to be one of the key solutions for future generation on-chip interconnects. However, energy efficiency is mainly limited by the losses incurred by the optical signals, which considerably reduces the optical power received by the photodetectors. In this paper we propose a differential transmission of the modulated signals, which contributes to improve the transmission of the optical signal power on the receiver side. With this approach, it is possible to reduce the input laser power and increase the energy efficiency of the optical communication. The approach is generic and can be applied to SWSR-, MWSR-, SWMR- and MWMR-like architectures

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

The future of computing beyond Moore's Law.

Moore's Law is a techno-economic model that has enabled the information technology industry to double the performance and functionality of digital electronics roughly every 2 years within a fixed cost, power and area. Advances in silicon lithography have enabled this exponential miniaturization of electronics, but, as transistors reach atomic scale and fabrication costs continue to rise, the classical technological driver that has underpinned Moore's Law for 50 years is failing and is anticipated to flatten by 2025. This article provides an updated view of what a post-exascale system will look like and the challenges ahead, based on our most recent understanding of technology roadmaps. It also discusses the tapering of historical improvements, and how it affects options available to continue scaling of successors to the first exascale machine. Lastly, this article covers the many different opportunities and strategies available to continue computing performance improvements in the absence of historical technology drivers. This article is part of a discussion meeting issue 'Numerical algorithms for high-performance computational science'

Large-Scale Optical Neural Networks based on Photoelectric Multiplication

Recent success in deep neural networks has generated strong interest in hardware accelerators to improve speed and energy consumption. This paper presents a new type of photonic accelerator based on coherent detection that is scalable to large ($N \gtrsim 10^6$) networks and can be operated at high (GHz) speeds and very low (sub-aJ) energies per multiply-and-accumulate (MAC), using the massive spatial multiplexing enabled by standard free-space optical components. In contrast to previous approaches, both weights and inputs are optically encoded so that the network can be reprogrammed and trained on the fly. Simulations of the network using models for digit- and image-classification reveal a "standard quantum limit" for optical neural networks, set by photodetector shot noise. This bound, which can be as low as 50 zJ/MAC, suggests performance below the thermodynamic (Landauer) limit for digital irreversible computation is theoretically possible in this device. The proposed accelerator can implement both fully-connected and convolutional networks. We also present a scheme for back-propagation and training that can be performed in the same hardware. This architecture will enable a new class of ultra-low-energy processors for deep learning.Comment: Text: 10 pages, 5 figures, 1 table. Supplementary: 8 pages, 5, figures, 2 table

Room Temperature InP DFB Laser Array Directly Grown on (001) Silicon

Fully exploiting the silicon photonics platform requires a fundamentally new approach to realize high-performance laser sources that can be integrated directly using wafer-scale fabrication methods. Direct band gap III-V semiconductors allow efficient light generation but the large mismatch in lattice constant, thermal expansion and crystal polarity makes their epitaxial growth directly on silicon extremely complex. Here, using a selective area growth technique in confined regions, we surpass this fundamental limit and demonstrate an optically pumped InP-based distributed feedback (DFB) laser array grown on (001)-Silicon operating at room temperature and suitable for wavelength-division-multiplexing applications. The novel epitaxial technology suppresses threading dislocations and anti-phase boundaries to a less than 20nm thick layer not affecting the device performance. Using an in-plane laser cavity defined by standard top-down lithographic patterning together with a high yield and high uniformity provides scalability and a straightforward path towards cost-effective co-integration with photonic circuits and III-V FINFET logic

Recent Trends and Considerations for High Speed Data in Chips and System Interconnects

This paper discusses key issues related to the design of large processing volume chip architectures and high speed system interconnects. Design methodologies and techniques are discussed, where recent trends and considerations are highlighted