21 research outputs found

    A Preliminary Performance Study of Architectural Support for Multithreading

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    Compiling for parallel multithreaded computation on symmetric multiprocessors

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 145-149).by Andrew Shaw.Ph.D

    Dynamic computation migration in distributed shared memory systems

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.Vita.Includes bibliographical references (p. 123-131).by Wilson Cheng-Yi Hsieh.Ph.D

    Partitioning non-strict languages for multi-threaded code generation

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 107-109).by Satyan R. Coorg.Ph.D

    The Named-State Register File

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    This thesis introduces the Named-State Register File, a fine-grain, fully-associative register file. The NSF allows fast context switching between concurrent threads as well as efficient sequential program performance. The NSF holds more live data than conventional register files, and requires less spill and reload traffic to switch between contexts. This thesis demonstrates an implementation of the Named-State Register File and estimates the access time and chip area required for different organizations. Architectural simulations of large sequential and parallel applications show that the NSF can reduce execution time by 9% to 17% compared to alternative register files

    Hybrid eager and lazy evaluation for efficient compilation of Haskell

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 208-220).This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.The advantage of a non-strict, purely functional language such as Haskell lies in its clean equational semantics. However, lazy implementations of Haskell fall short: they cannot express tail recursion gracefully without annotation. We describe resource-bounded hybrid evaluation, a mixture of strict and lazy evaluation, and its realization in Eager Haskell. From the programmer's perspective, Eager Haskell is simply another implementation of Haskell with the same clean equational semantics. Iteration can be expressed using tail recursion, without the need to resort to program annotations. Under hybrid evaluation, computations are ordinarily executed in program order just as in a strict functional language. When particular stack, heap, or time bounds are exceeded, suspensions are generated for all outstanding computations. These suspensions are re-started in a demand-driven fashion from the root. The Eager Haskell compiler translates Ac, the compiler's intermediate representation, to efficient C code. We use an equational semantics for Ac to develop simple correctness proofs for program transformations, and connect actions in the run-time system to steps in the hybrid evaluation strategy.(cont.) The focus of compilation is efficiency in the common case of straight-line execution; the handling of non-strictness and suspension are left to the run-time system. Several additional contributions have resulted from the implementation of hybrid evaluation. Eager Haskell is the first eager compiler to use a call stack. Our generational garbage collector uses this stack as an additional predictor of object lifetime. Objects above a stack watermark are assumed to be likely to die; we avoid promoting them. Those below are likely to remain untouched and therefore are good candidates for promotion. To avoid eagerly evaluating error checks, they are compiled into special bottom thunks, which are treated specially by the run-time system. The compiler identifies error handling code using a mixture of strictness and type information. This information is also used to avoid inlining error handlers, and to enable aggressive program transformation in the presence of error handling.by Jan-Willem Maessen.Ph.D

    Estudo do relaxamento da condição de dupla entrada em uma arquitetura hibrida

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    Orientador: Arthur João CattoArquivo incompleto - falta página 118Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Matematica, Estatistica e Ciencia da ComputaçãoResumo: As arquiteturas híbridas resultantes da junção das melhores características dos modelos von Neumann e de fluxo de dados formam uma nova classe de sistemas .paralelos de alto desempenho. A máquina MX é uma proposta preliminar e abstrata de uma arquitetura híbrida que utiliza a técnica de Fluxo de Dados para desmembrar programas em blocos de instruções limitados ao máximo de dois operandos de entrada. Este trabalho apresenta uma análise de técnicas mais eficientes de desmembramento para arquiteturas híbridas cujo modelo de execução não impõe restrições quanto ao número de operandos de entrada de um bloco de instruções. A escalabilidade da máquina MX e a influência do tamanho do bloco de instruções no seu desempenho sustentam a proposta de relaxamento da restrição da dupla entrada de um bloco de instruções, com o propósito de aumentar o desempenho da MX, conservando as suas características arquiteturais.Abstract: Hybrid architectures which result from joining the best features of the von Neumann and data flow computational models give rise to a new class of high performance parallel systems. The MX machine is a preliminary and abstract hybrid architecture proposal which resorts to data flow techniques for partitioning programs into instruction streams which are limited to two entry operands. This thesis presents an analysis of more efficient partitioning techniques for hybrid architectures whose execution model does not restrict the number of entry operands in an instruction stream. The scalability of the MX machine and the influence of the instruction stream size on its performance support a proposal for waiving the double entry limit to an instruction stream, aiming at increasing the performance of the MX machine, without altering its architectural characteristics.MestradoMestre em Ciência da Computaçã
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