A high speed serializer/deserializer design

A Serializer/Deserializer (SerDes) is a circuit that converts parallel data into a serial stream and vice versa. It helps solve clock/data skew problems, simplifies data transmission, lowers the power consumption and reduces the chip cost. The goal of this project was to solve the challenges in high speed SerDes design, which included the low jitter design, wide bandwidth design and low power design. A quarter-rate multiplexer/demultiplexer (MUX/DEMUX) was implemented. This quarter-rate structure decreases the required clock frequency from one half to one quarter of the data rate. It is shown that this significantly relaxes the design of the VCO at high speed and achieves lower power consumption. A novel multi-phase LC-ring oscillator was developed to supply a low noise clock to the SerDes. This proposed VCO combined an LC-tank with a ring structure to achieve both wide tuning range (11%) and low phase noise (-110dBc/Hz at 1MHz offset). With this structure, a data rate of 36 Gb/s was realized with a measured peak-to-peak jitter of 10ps using 0.18microm SiGe BiCMOS technology. The power consumption is 3.6W with 3.4V power supply voltage. At a 60 Gb/s data rate the simulated peak-to-peak jitter was 4.8ps using 65nm CMOS technology. The power consumption is 92mW with 2V power supply voltage. A time-to-digital (TDC) calibration circuit was designed to compensate for the phase mismatches among the multiple phases of the PLL clock using a three dimensional fully depleted silicon on insulator (3D FDSOI) CMOS process. The 3D process separated the analog PLL portion from the digital calibration portion into different tiers. This eliminated the noise coupling through the common substrate in the 2D process. Mismatches caused by the vertical tier-to-tier interconnections and the temperature influence in the 3D process were attenuated by the proposed calibration circuit. The design strategy and circuits developed from this dissertation provide significant benefit to both wired and wireless applications

Voltage controlled oscillator for mm-wave radio systems

Abstract. The advancement in silicon technology has accelerated the development of integrated millimeter-wave transceiver systems operating up to 100 GHz with sophisticated functionality at a reduced consumer cost. Due to the progress in the field of signal processing, frequency modulated continuous wave (FMCW) radar has become common in recent years. A high-performance local oscillator (LO) is required to generate reference signals utilized in these millimeter-wave radar transceivers. To accomplish this, novel design techniques in fundamental voltage controlled oscillators (VCO) are necessary to achieve low phase noise, wide frequency tuning range, and good power efficiency. Although integrated VCOs have been studied for decades, as we move higher in the radio frequency spectrum, there are new trade-offs in the performance parameters that require further characterization. The work described in this thesis aims to design a fully integrated fundamental VCO targeting to 150 GHz, i.e., D-Band. The purpose is to observe and analyze the design limitations at these high frequencies and their corresponding trade-offs during the design procedure. The topology selected for this study is the cross-coupled LC tank VCO. For the study, two design topologies were considered: a conventional cross-coupled LC tank VCO and an inductive divider cross-coupled LC tank VCO. The conventional LC tank VCO yields better performance in terms of phase noise and tuning range. It is observed that the VCO is highly sensitive to parasitic contributions by the transistors, and the layout interconnects, thus limiting the targeted frequency range. The dimensions of the LC tank and the transistors are selected carefully. Moreover, the VCO performance is limited by the low Q factor of the LC tank governed by the varactor that is degrading the phase noise performance and the tuning range, respectively. The output buffer loaded capacitance and the core power consumption of the VCO are optimized. The layout is drawn carefully with strategies to minimize the parasitic effects. Considering all the design challenges, a 126 GHz VCO with a tuning range of 3.9% is designed. It achieves FOMT (Figure-of-merit) of -172 dBc/Hz, and phase noise of -99.14 dBc/Hz at 10 MHz offset, Core power consumption is 8.9 mW from a 1.2 V supply. Just falling short of the targeted frequency, the design is suitable for FMCW radar applications for future technologies. The design was done using Silicon-on-Insulator (SOI) CMOS technology

Design and Analysis of Low-power Millimeter-Wave SiGe BiCMOS Circuits with Application to Network Measurement Systems

Interest in millimeter (mm-) wave frequencies covering the spectrum of 30-300 GHz has been steadily increasing. Advantages such as larger absolute bandwidth and smaller form-factor have made this frequency region attractive for numerous applications, including high-speed wireless communication, sensing, material science, health, automotive radar, and space exploration. Continuous development of silicon-germanium heterojunction bipolar transistor (SiGe HBT) and associated BiCMOS technology has achieved transistors with fT/fmax of 505/720 GHz and integration with 55 nm CMOS. Such accomplishment and predictions of beyond THz performance have made SiGe BiCMOS technology the most competitive candidate for addressing the aforementioned applications. Especially for mobile applications, a critical demand for future mm-wave applications will be low DC power consumption (Pdc), which requires a substantial reduction of supply voltage and current. Conventionally, reducing the supply voltage will lead to HBTs operating close to or in the saturation region, which is typically avoided in mm-wave circuits due to expectated performance degradation and often inaccurate models. However, due to only moderate speed reduction at the forward-biased base-collector voltage (VBC) up to 0.5 V and the accuracy of the compact model HICUM/L2 also in saturation, low-power mm-wave circuits with SiGe HBTs operating in saturation offer intriguing benefits, which have been explored in this thesis based on 130 nm SiGe BiCMOS technologies: • Different low-power mm-wave circuit blocks are discussed in detail, including low-noise amplifiers (LNAs), down-conversion mixers, and various frequency multipliers covering a wide frequency range from V-band (50-75 GHz) to G-band (140-220 GHz). • Aiming at realizing a better trade-off between Pdc and RF performance, a drastic decrease in supply voltage is realized with forward-biased VBC, forcing transistors of the circuits to operate in saturation. • Discussions contain the theoretical analysis of the key figure of merits (FoMs), topology and bias selection, device sizing, and performance enhancement techniques. • A 173-207 GHz low-power amplifier with 23 dB gain and 3.2 mW Pdc, and a 72-108 GHz low-power tunable amplifier with 10-23 dB gain and 4-21 mW Pdc were designed. • A 97 GHz low-power down-conversion mixer was presented with 9.6 dB conversion gain (CG) and 12 mW Pdc. • For multipliers, a 56-66 GHz low-power frequency quadrupler with -3.6 dB peak CG and 12 mW Pdc, and a 172-201 GHz low-power frequency tripler with -4 dB peak CG and 10.5 mW Pdc were realized. By cascading these two circuits, also a 176-193 GHz low-power ×12 multiplier was designed, achieving -11 dBm output power with only 26 mW Pdc. • An integrated 190 GHz low-power receiver was designed as one receiving channel of a G-band frequency extender specifically for a VNA-based measurement system. Another goal of this receiver is to explore the lowest possible Pdc while keeping its highly competitive RF performance for general applications requiring a wide LO tuning range. Apart from the low-power design method of circuit blocks, the careful analysis and distribution of the receiver FoMs are also applied for further reduction of the overall Pdc. Along this line, this receiver achieved a peak CG of 49 dB with a 14 dB tunning range, consuming only 29 mW static Pdc for the core part and 171 mW overall Pdc, including the LO chain. • All designs presented in this thesis were fabricated and characterized on-wafer. Thanks to the accurate compact model HICUM/L2, first-pass access was achieved for all circuits, and simulation results show excellent agreement with measurements. • Compared with recently published work, most of the designs in this thesis show extremely low Pdc with highly competitive key FoMs regarding gain, bandwidth, and noise figure. • The observed excellent measurement-simulation agreement enables the sensitivity analysis of each design for obtaining a deeper insight into the impact of transistor-related physical effects on critical circuit performance parameters. Such studies provide meaningful feedback for process improvement and modeling development.:Table of Contents Kurzfassung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of symbols and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Technology 7 2.1 Fabrication Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 SiGe HBT performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 B11HFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 SG13G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.4 SG13D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Commonly Used Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Grounded-sidewall-shielded microstrip line . . . . . . . . . . . . . . . . . . 12 2.2.2 Zero-impedance Transmission Line . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.3.1 Active Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.3.2 Passive Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Low-power Low-noise Amplifiers 25 3.1 173-207 GHz Ultra-low-power Amplifier . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.1 Topology Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.2 Bias Dependency of the Small-signal Performance . . . . . . . . . . . . . 27 3.1.2.1 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1.2.2 Bias vs Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.2.3 Bias vs Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.2.4 Bias vs Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.3 Bias selection and Device sizing . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.1 Bias Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.2 Device Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1.4 Performance Enhancement Technologies . . . . . . . . . . . . . . . . . . . 41 3.1.4.1 Gm-boosting Inductors . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.4.2 Stability Enhancement . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.4.3 Noise Improvement . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1.5 Circuit Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.1 Layout Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.2 Inductors Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.5.3 Dual-band Matching Network . . . . . . . . . . . . . . . . . . . 48 3.1.5.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.6 Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2 72-108 GHz Low-Power Tunable Amplifier . . . . . . . . . . . . . . . . . . . . . . 55 3.2.1 Configuration, Sizing, and Bias Tuning Range . . . . . . . . . . . . . . . . 55 3.2.2 Regional Matching Network . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.1 Impedance Variation . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.2 Regional Matching Network Design . . . . . . . . . . . . . . . . 60 3.2.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4 Low-power Down-conversion Mixers 73 4.1 97 GHz Low-power Down-conversion Mixer . . . . . . . . . . . . . . . . . . . . . 74 4.1.1 Mixer Design and Implementation . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.1 Mixer Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.2 Bias Selection and Device Sizing . . . . . . . . . . . . . . . . . . 77 4.1.1.3 Mixer Implementation . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.2 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.1 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5 Low-power Multipliers 87 5.1 General Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.2 56-66 GHz Low-power Frequency Quadrupler . . . . . . . . . . . . . . . . . . . . 89 5.3 172-201 GHz Low-power Frequency Tripler . . . . . . . . . . . . . . . . . . . . . 93 5.4 176-193 GHz Low-power ×12 Frequency Multiplier . . . . . . . . . . . . . . . . . 96 5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6 Low-power Receivers 101 6.1 Receiver Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2 LO Chain (×12) Integrated 190 GHz Low-Power Receiver . . . . . . . . . . . . . 104 6.2.1 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2.2 Low-power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2.3 Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.1 LNA and LO DA . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.2 Tunable Mixer and IF BA . . . . . . . . . . . . . . . . . . . . . 111 6.2.3.3 65 GHz (V-band) Quadrupler . . . . . . . . . . . . . . . . . . . 116 6.2.3.4 G-band Tripler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.4 Receiver Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . 123 6.2.5 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.2.6 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7 Conclusions 133 7.1 Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.2 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Bibliography 135 List of Figures 149 List of Tables 157 A Derivation of the Gm 159 A.1 Gm of standard cascode stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 A.2 Gm of cascode stage with Lcas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 A.3 Gm of cascode stage with Lb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 B Derivation of Yin in the stability analysis 163 C Derivation of Zin and Zout 165 C.1 Zin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 C.2 Zout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 D Derivation of the cascaded oP1dB 169 E Table of element values for the designed circuits 17

Passive und aktive Radio Frequency Identification Tags im 60-GHz-Band

Die Einführung des millimeter-Wellen-Bandes eröffnet neue Perspektiven für die Radio Frequency Identification (RFID) Kommunikationssysteme. Der Enwurf des Systems im 60-GHz-Band ermöglicht die Implementierung der On-Chip Antenne und darüber hinaus die Implementierung eines RFID-Tags auf einem einzigen Chip. Dennoch ist es aufgrund der gesetzlichen Beschränkung der effektiven isotropen Strahlungsleistung (EIRP) des Lesegeräts und der erhöhten Freiraum-Dielektrikumsverluste eine Herausforderung, eine zuverlässige Kommunikationsreichweite von mehreren Millimetern zu erreichen. Neue Lösungen sind für jeden Block sowohl im Lesegerät als auch im Single-Chip-Tag erforderlich. Obwohl das Lesegerät batteriebetrieben ist, ist es immer noch eine Herausforderung, die maximal zulässigen 20 dBm IERP des Lesersenders energieeffizient zu erzeugen. Darüber hinaus sollte der Empfänger einen ausreichenden Dynamikbereich haben, um das vom Tag kommende Signal zu erkennen. Auf der Tag-Seite sind die Hauptherausforderungen das Co-Design der effizienten On-Chip-Antennen-Implementierung, die hochempfindliche Gleichrichter-Implementierung und das Rückkommunikationskonzept. Diese Arbeit konzentriert sich auf die Machbarkeitsstudie des Single-Chip-RFID-Tags und die Implementierung im Millimeterwellenbereich. Es werden zwei Rückkommunikationskonzepte untersucht - Backscattering-Rückkommunikation und eine Kommunikation unter Verwendung von Ultra-Low-Power (ULP) Radios. Beide werden in einem 22 nm FDSOI Prozess auf einem Substrat mit geringem Widerstand implementiert. Beide Tags arbeiten mit einer Versorgungsspannung von 0,4 V, um die Kommunikationsreichweite zu maximieren. Die Link-Budgets sind so ausgelegt, dass sie die regulatorischen Beschränkungen einhalten. Die Auswahl des Technologieknotens wird begründet. Verschiedene Aspekte im Zusammenhang mit der Technologie werden diskutiert, wie z. B. Geräteleistung, passiver Qualitätsfaktor, Leistungsdichte der Kondensatoren. Der Backscattering RFID-Tag wird zuerst entworfen, da er eine relativ einfachere Topologie hat. Die Probleme der Gleichrichterempfindlichkeit im Rahmen des analogen Frontends, der On-Chip-Antenneneffizienz und der konjugierten Anpassung beider werden untersucht. Eine Kommunikationsreichweite von 5 mm wird angestrebt und realisiert. Um die Kommunikationsreichweite weiter zu erhöhen, wird in der zweiten Phase ein Tag mit einer aktiven Rückkommunikation implementiert. Hier wird die Gleichrichterempfindlichkeit weiter verbessert. Es wird ein 0,4V ULP Radio entworfen, das sich die Antenne mit dem Gleichrichter über einen Single-Pole- Double-Through (SPDT) Schalter teilt. Ein Abstand von 2 cm erwies sich als realisierbar, wobei die gesetzlichen Bestimmungen eingehalten und der dynamische Bereich des Leseempfängers nicht überschritten wurde. Es wird die höchste normalisierte Kommunikationsreichweite pro Leser-EIRP erreicht. Weitere Verbesserungsmöglichkeiten werden diskutiert

Silicon Germanium BiCMOS Integrated Circuits for Scalable Cryogenic Sensing Applications

This dissertation is focused on an investigation of BiCMOS cryogenic low noise amplifiers (LNAs) based on Silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for simultaneous low noise and low power design and also taking advantage of CMOS circuitry for adding flexibility to the LNA design. Cryogenic LNAs\u27 scalability challenges are discussed and addressed in the dissertation. To achieve that, first, HBTs of three state-of-the-art technologies are characterized and modeled at cryogenic temperature. It is shown that SiGe HBT provides a promising compromise of noise temperature, power consumption, and bandwidth. Moreover, a scalable on-chip approach is proposed and verified for biasing of SiGe HBTs based LNAs. Finally, the first cryogenic re-configurable LNA is designed, implemented, and measured

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

CMOS Front-End Circuits in 45-nm SOI Suitable for Modular Phased-Array 60-GHz Radios

Next Fifth-generation (5G) wireless technologies enabling ultra-wideband spectrum availability and increased system capacity can achieve multi-gigabit/s (Gbps) data rates suitable for ultra-high-speed internet access around the 60-GHz band (i.e., Wi-Gig Technology). This mm-wave band is unlicensed and experiences high propagation power losses. Therefore, it is suitable for short-range communications and requires antenna arrays to satisfy the link budget requirements. Half-duplex reconfigurable phased-array transceivers require wideband, low-cost, highly integrated front-end circuits such as bilateral RF switches, low-noise/power amplifiers, passive RF splitters/combiners, and phase shifters implemented in deep sub-micron CMOS. In this dissertation, analysis, design, and verification of essential CMOS front-end components are covered and fabricated in GlobalFoundries 45-nm RF-SOI CMOS technology. Firstly, a fully-differential, single-pole, single-throw (SPST) switch capable of high isolation in broadband CMOS transceivers is described. The SPST switch realizes better than 50-dB isolation (ISO) across DC to 43 GHz while maintaining an insertion loss (IL) below 3 dB. Measured RF input power for 1-dB compression (IP1dB) of the IL is +19.6 dBm, and the measured input third-order intercept point (IIP3) is +30.4 dBm (both assuming differential inputs at 20 GHz). The prototype has an active area of 0.0058 mm^2. Secondly, a single-pole double-throw (SPDT) switch is implemented using the SPST concept by using a balun to convert the shared differential path to a single-ended antenna port. The SPDT simulations predict less than 3.5-dB IL and greater than 40-dB ISO across 55 to 65 GHz frequency band. An IP1dB of +21 dBm is expected from large-signal simulations. The prototype has an active area of 0.117 mm^2. Thirdly, a fully-differential switched-LC topology adopted with slow-wave artificial transmission line concept, and phase inversion network is described for a 360-degree phase shift range with 11.25-degree phase resolution. The average IL of the complete phase shifter is 5.3 dB with less than 1-dB rms IL error. Furthermore, the IP1dB of the phase shifter is +16 dBm. The prototype has an active area of 0.245 mm^2. Lastly, a fully-differential, 2-stage, common-source (CS) low-noise amplifier (LNA) is developed with wideband matching from 57.8 GHz to 67 GHz, a maximum simulated forward power gain of 20.8 dB, and a minimum noise figure of 3.07 dB. The LNA consumes 21 mW and predicts an OP1dB of 4.8 dBm from the 1-V supply. The LNA consumes an active area of 0.028 mm^2

Analysis and Design of a Sub-THz Ultra-Wideband Phased-Array Transmitter

This thesis investigates circuits and systems for broadband high datarate transmitter systems in the millimeter-wave (mm-wave) spectrum. During the course of this dissertation, the design process and characterization of a power efficient and wideband binary phase-shift keying (BPSK) transmitter integrated circuit (IC) with local oscillator (LO) frequency multiplication and 360° phase control for beam steering is studied. All required circuit blocks are designed based on the theoretical analysis of the underlying principles, optimized, fabricated and characterized in the research laboratory targeting low power consumption, high efficiency and broadband operation. The phase-controlled push-push (PCPP) architecture enabling frequency multiplication by four in a single stage is analytically studied and characterized finding an optimum between output power and second harmonic suppression depending on the input amplitude. A PCPP based LO chain is designed. A circuit is fabricated establishing the feasibility of this architecture for operation at more than 200 GHz. Building on this, a second circuit is designed, which produces among the highest saturated output powers at 2 dBm. At less than 100 mW of direct current (DC) power consumption, this results in a power-added efficiency (PAE) of 1.6 % improving the state of the art by almost 30 %. Phase-delayed and time-delayed approaches to beam steering are analyzed, identifying and discussing design challenges like area consumption, signal attenuation and beam squint. A 60 GHz active vector-sum phase-shifter with high gain of 11.3 dB and output power of 5 dBm, improving the PAE of the state of the art by a factor of 30 achieving 6.29 %, is designed. The high gain is possible due to an optimization of the orthogonal signal creation stage enabled by studying and comparing different architectures leading to a trade off of lower signal attenuation for higher area consumption in the chosen electromagnetic coupler. By combining this with a frequency quadrupler, a phase steering enabled LO chain for operation at 220 GHz is created and characterized, confirming the preceding analysis of the phase-frequency relation during multiplication. It achieves a power gain of 21 dB, outperforming comparable designs by 25 dB. This allows the combination of phase control, frequency multiplication and pre-amplification. The radio frequency (RF) efficiency is increased 40-fold to 0.99 %, with a total power consumption of 105 mW. Motivated by the distorting effect of beam squint in phase-delayed broadband array systems, a novel analog hybrid beam steering architecture is devised, combining phase-delayed and time-delayed steering with the goal of reducing the beam squint of phase-delayed systems and large area consumption of time-delayed circuits. An analytical design procedure is presented leading to the research finding of a beam squint reduction potential of more than 83 % in an ideal system. Here, the increase in area consumption is outweighed by the reduction in beam squint. An IC with a low power consumption of 4.3 mW has been fabricated and characterized featuring the first time delay circuit operating at above 200 GHz. By producing most of the beam direction by means of time delay the beam squinting can be reduced by more than 75 % in measurements while the subsequent phase shifter ensures continuous beam direction control. Together, the required silicon area can be reduced to 43 % compared to timedelayed systems in the same frequency range. Based on studies of the optimum signal feeding and input matching of a Gilbert cell, an ultra-wideband, low-power mixer was designed. A bandwidth of more than 100 GHz was achieved exceeding the state of the art by 23 %. With a conversion gain of –13 dB, this enables datarates of more than 100 Gbps in BPSK operation. The findings are consolidated in an integrated transmitter operating around 246 GHz doubling the highest published measured datarates of transmitters with LO chain and power amplifier in BPSK operation to 56 Gbps. The resulting transmitter efficiency of 7.4 pJ/bit improves the state of the art by 70 % and 50 % over BPSK and quadrature phaseshift keying (QPSK) systems, respectively. Together, the results of this work form the basis for low-power and efficient next-generation wireless applications operating at many times the datarates available today.:Abstract 3 Zusammenfassung 5 List of Symbols 11 List of Acronyms 17 Prior Publications 19 1. Introduction 21 1.1. Motivation........................... 21 1.2. Objective of this Thesis ................... 25 1.3. Structure of this Thesis ................... 27 2. Overview of Employed Technologies and Techniques 29 2.1. IntegratedCircuitTechnology................ 29 2.2. Transmission Lines and Passive Structures . . . . . . . . 35 2.3. DigitalModulation ...................... 41 3. Frequency Quadrupler 45 3.1. Theoretical Analysis of Frequency Multiplication Circuits 45 3.2. Phase-Controlled Push-Push Principle for Frequency Quadrupling.......................... 49 3.3. Stand-alone Phase-Controlled Push-Push Quadrupler . 60 3.4. Phase-Controlled Push-Push Quadrupler based LO-chain with High Output Power ............... 72 9 4. Array Systems and Dynamic Beam Steering 91 4.1. Theoretical Analysis of BeamSteering. . . . . . . . . . . 95 4.2. Local Oscillator Phase Shifting with Vector-Modulator PhaseShifters......................... 107 4.3. Hybrid True-Time and Phase-Delayed Beam Steering . 131 5. Ultra-Wide Band Modulator for BPSK Operation 155 6. Broadband BPSK Transmitter System for Datarates up to 56 Gbps 167 6.1. System Architecture ..................... 168 6.2. Measurement Technique and Results . . . . . . . . . . . 171 6.3. Summary and performance comparison . . . . . . . . . 185 7. Conclusion and Outlook 189 A. Appendix 195 Bibliography 199 List of Figures 227 Note of Thanks 239 Curriculum Vitae 241Diese Dissertation untersucht Schaltungen und Systeme für breitbandige Transmittersysteme mit hoher Datenrate im Millimeterwellen (mm-wave) Spektrum. Im Rahmen dieser Arbeit werden der Entwurfsprozess und die Charakterisierung eines leistungseffizienten und breitbandigen integrierten Senders basierend auf binärer Phasenumtastung (BPSK) mit Frequenzvervielfachung des Lokaloszillatorsignals und 360°-Phasenkontrolle zur Strahlsteuerung untersucht. Alle erforderlichen Schaltungsblöcke werden auf Grundlage von theoretischen Analysen der zugrundeliegenden Prinzipien entworfen, optimiert, hergestellt und im Forschungslabor charakterisiert, mit den Zielen einer niedrigen Leistungsaufnahme, eines hohen Wirkungsgrades und einer möglichst großen Bandbreite. Die phasengesteuerte Push-Push (PCPP)-Architektur, welche eine Frequenzvervierfachung in einer einzigen Stufe ermöglicht, wird analytisch untersucht und charakterisiert. Dabei wird ein Optimum zwischen Ausgangsleistung und Unterdrückung der zweiten Harmonischen des Eingangssignals in Abhängigkeit von der Eingangsamplitude gefunden. Es wird eine LO-Kette auf PCPP-Basis entworfen. Eine Schaltung wird präsentiert, die die Machbarkeit dieser Architektur für den Betrieb bei mehr als 200 GHz nachweist. Darauf aufbauend wird eine zweite Schaltung entworfen, die mit 2 dBm eine der höchsten publizierten gesättigten Ausgangsleistungen erzeugt. Mit einer Leistungsaufnahme von weniger als 100mW ergibt sich ein Leistungswirkungsgrad (PAE) von 1.6 %, was den Stand der Technik um fast 30 % verbessert. Es werden phasenverzögerte und zeitverzögerte Ansätze zur Steuerung der Strahlrichtung analysiert, wobei Entwicklungsherausforderungen wie Flächenverbrauch, Signaldämpfung und Strahlschielen identifiziert und diskutiert werden. Ein aktiver Vektorsummen-Phasenschieber mit hoher Verstärkung von 11.3 dB und einer Ausgangsleistung von 5 dBm, der mit einer PAE von 6.29 % den Stand der Technik um den Faktor 30 verbessert, wird entworfen. Die hohe Verstärkung ist zum Teil auf eine Optimierung der orthogonalen Signalerzeugungsstufe zurückzuführen, die durch die Untersuchung und den Vergleich verschiedener Architekturen ermöglicht wird. Bei der Entscheidung für einen elektromagnetischen Koppler rechtfertigt die geringere Signaldämpfung einen höheren Flächenverbrauch. Durch die Kombination mit einem Frequenzvervierfacher wird eine LO-Kette mit Phasensteuerung für den Betrieb bei 220 GHz geschaffen und charakterisiert, was die vorangegangene Analyse der Phasen-FrequenzBeziehung während der Multiplikation bestätigt. Sie erreicht einen Leistungsgewinn von 21 dB und übertrifft damit vergleichbare Designs um 25dB. Dies ermöglicht die Kombination von Phasensteuerung, Frequenzvervielfachung und Vorverstärkung. Der HochfrequenzWirkungsgrad wird um das 40-fache auf 0.99 % bei einer Gesamtleistungsaufnahme von 105 mW gesteigert. Motiviert durch den verzerrenden Effekt des Strahlenschielens in phasengesteuerten Breitbandarraysystemen, wird eine neuartige analoge hybride Strahlsteuerungsarchitektur untersucht, die phasenverzögerte und zeitverzögerte Steuerung kombiniert. Damit wird sowohl das Strahlenschielen phasenverzögerter Systeme als auch der große Flächenverbrauch zeitverzögerter Schaltungen reduziert. Es wird ein analytisches Entwurfsverfahren vorgestellt, das zu dem Forschungsergebnis führt, dass in einem idealen System ein Potenzial zur Reduktion des Strahlenschielens von mehr als 83 % besteht. Dabei wird die Zunahme des Flächenverbrauchs durch die Verringerung des Strahlenschielens aufgewogen. Es wird ein IC mit einer geringen Leistungsaufnahme von 4.3mW hergestellt und charakterisiert. Dabei wird die erste Zeitverzögerungsschaltung entworfen, die bei über 200 GHz arbeitet. Durch die Erzeugung eines Großteils der Strahlrichtung mittels Zeitverzögerung kann das Schielen des Strahls bei Messungen um mehr als 75% reduziert werden, während der nachfolgende Phasenschieber eine kontinuierliche Steuerung der Strahlrichtung gewährleistet. Insgesamt kann die benötigte Siliziumfläche im Vergleich zu zeitverzögerten Systemen im gleichen Frequenzbereich auf 43 % reduziert werden. Auf der Grundlage von Studien zur optimalen Signaleinspeisung und Eingangsanpassung einer Gilbert-Zelle wird ein Ultrabreitband-Mischer mit geringem Stromverbrauch entworfen. Dieser erreicht eine Ausgangsbandbreite von mehr als 100 GHz, die den Stand der Technik um 23% übertrifft. Bei einer Wandlungsverstärkung von –13dB ermöglicht dies Datenraten von mehr als 100 Gbps im BPSK-Betrieb. Die Erkenntnisse werden in einem integrierten, breitbandigen Sender konsolidiert, der um 246 GHz arbeitet und die höchsten veröffentlichten gemessenen Datenraten für Sender mit LO-Signalkette und Leistungsverstärker im BPSK-Betrieb auf 56 Gbps verdoppelt. Die daraus resultierende Transmitter-Effizienz von 7.4 pJ/bit verbessert den Stand der Technik um 70 % bzw. 50 % gegenüber BPSKund Quadratur Phasenumtastung (QPSK)-Systemen. Zusammen bilden die Ergebnisse dieser Arbeit die Grundlage für stromsparende, effiziente, mobile Funkanwendungen der nächsten Generation mit einem Vielfachen der heute verfügbaren Datenraten.:Abstract 3 Zusammenfassung 5 List of Symbols 11 List of Acronyms 17 Prior Publications 19 1. Introduction 21 1.1. Motivation........................... 21 1.2. Objective of this Thesis ................... 25 1.3. Structure of this Thesis ................... 27 2. Overview of Employed Technologies and Techniques 29 2.1. IntegratedCircuitTechnology................ 29 2.2. Transmission Lines and Passive Structures . . . . . . . . 35 2.3. DigitalModulation ...................... 41 3. Frequency Quadrupler 45 3.1. Theoretical Analysis of Frequency Multiplication Circuits 45 3.2. Phase-Controlled Push-Push Principle for Frequency Quadrupling.......................... 49 3.3. Stand-alone Phase-Controlled Push-Push Quadrupler . 60 3.4. Phase-Controlled Push-Push Quadrupler based LO-chain with High Output Power ............... 72 9 4. Array Systems and Dynamic Beam Steering 91 4.1. Theoretical Analysis of BeamSteering. . . . . . . . . . . 95 4.2. Local Oscillator Phase Shifting with Vector-Modulator PhaseShifters......................... 107 4.3. Hybrid True-Time and Phase-Delayed Beam Steering . 131 5. Ultra-Wide Band Modulator for BPSK Operation 155 6. Broadband BPSK Transmitter System for Datarates up to 56 Gbps 167 6.1. System Architecture ..................... 168 6.2. Measurement Technique and Results . . . . . . . . . . . 171 6.3. Summary and performance comparison . . . . . . . . . 185 7. Conclusion and Outlook 189 A. Appendix 195 Bibliography 199 List of Figures 227 Note of Thanks 239 Curriculum Vitae 24

Développement d'une architecture innovante de récepteur radar à 77 GHz et démonstration en CMOS 28 nm FDSOI

Grâce à sa capacité à détecter des cibles éloignées malgré une mauvaise visibilité, le radar automobile à 77 GHz joue un rôle important dans l'aide à la conduite. L'utilisation des fréquences millimétriques offre une bonne résolution et une importante capacité d'intégration des circuits. C'est aussi un défi car il faut satisfaire un cahier des charges exigeant sur le bruit et la linéarité du récepteur. Les technologies SiGe BiCMOS ont été les premières utilisées pour la conception de récepteurs radar à 77 GHz. De bons résultats ont été obtenus en se basant sur des architectures utilisant des mélangeurs actifs. Cependant l'utilisation des technologie BiCMOS se traduisait par une consommation élevée, une faible capacité d'intégration et des coûts de production importants. Récemment, l'intégration des procédés CMOS menant à l'augmentation des fréquences de transition rend ces technologies plus attractives pour les applications nécessitant un faible coût et la cointégration de plusieurs fonctions au sein d'une même puce. La littérature sur les récepteurs radars en technologie CMOS à 77 GHz montre que les architectures inspirées par les technologies BiCMOS ne sont pas pertinentes pour cette application. Le but de cette thèse et de montrer que l'utilisation de techniques propres aux technologie CMOS comme l'échantillonnage et l'utilisation de portes logiques permet d'obtenir de très bonnes performances. Dans ce travail, deux nouvelles architectures de récepteurs radars basées sur le principe d'échantillonnage sont proposées. La première architecture est basée sur un mélangeur passif échantillonné qui permet d'obtenir un très bon compromis bruit/linéarité. La seconde exploite les propriétés des mélangeurs sous-échantillonnés afin utiliser une fréquence d'OL trois fois inférieure à la fréquence RF offrant ainsi de très intéressantes simplifications au niveau de la chaîne de distribution du signal d'OL du récepteur. Le contexte de cette étude est expliqué dans le 1er chapitre qui présente les exigences de conception liées à l'application radar et fourni une analyse de l'état de l'art des récepteurs à 77 GHZ. Le chapitre suivant décrit le principe de fonctionnement et l'implémentation d'un mélangeur échantillonné à 77 GHz en technologie CMOS 28- nm FDSOI. Une topologie de mélangeur sous-échantillonné utilisant une fréquence d'OL de 26 GHz pour convertir des signaux RF autour de 77 GHz est ensuite détaillée dans le chapitre 3. Le chapitre 4 conclut cette étude en détaillant l'intégration des mélangeurs étudiés dans les chapitres précédents avec un amplificateur faible bruit dans différents récepteurs radars. Ces architectures de récepteurs basées sur l'échantillonnage sont ensuite comparées entre elles et avec l'état de l'art montrant ainsi leurs avantages et inconvénients. Les résultats de cette comparaison confirment l'intérêt des techniques d'échantillonnage pour la conversion de fréquence dans le cadre de l'application radar.With its ability to detect distant targets under harsh visibility conditions, the 77 GHz automotive radar plays a key role in driving safety. Using mm-wave frequencies allow a good range resolution, a better circuit integration and a wide modulation bandwidth. This is also a challenge for circuit designers who must fulfill stringent requirements especially on the receiver front-end. First 77 GHz radar receivers were manufactured with SiGe BiCMOS processes benefiting from the high transition frequency and high breakdown voltage of Hetero-junction Bipolar Transistors (HBT). Good results have been achieved with active-mixer-based architectures, but these technologies suffer from high power consumptions, limited integration capacity and large production cost. More recently, the scaling down of CMOS processes (coming together with the increase of the transition frequency of the transistors) makes CMOS a good candidate for 77 GHz circuit design, especially when cost target requires single chip solutions. The literature related to CMOS radar receivers highlights that receivers based on BiCMOS architectures generally show poor performances. The aim of this work is to demonstrate that using CMOS specific technics such as sampling and the use of high-speed digital gates should enhance the performance of the receivers. In this work, two innovative radar receiver architectures based on the sampling principle are proposed. The first one shows that this principle can be extended to millimeter wave frequencies to benefit from a very good noise/linearity trade-off. While the second one uses this principle to converts a 77 GHz RF signal by using a 26 GHz LO frequency thus simplifying the LO distribution chain of the receiver. The background of this study is introduced in the chapter 1 presenting the design trade-off related to the 77 GHz radar receiver and provides a review of the existing solutions. The following chapter describes the sampling mixer principle and the implementation of a 77 GHz sampling mixer in 28-nm FDSOI CMOS technology. Then, a sub- sampling mixer topology allowing to convert an RF signal around 77 GHz using a 26 GHz LO frequency is detailed in the chapter 3. The chapter 4 draws the conclusion of this study by showing the implementation of the two proposed sampling-based mixers with a low noise amplifier in 77 GHz front ends. These receiver architectures are compared with the state of the art highlighting the strengths and weaknesses of the proposed solutions. The results of this study demonstrates that using sampling for down conversion can be convenient to address millimeter-wave frequency applications