20 research outputs found

    Modelling and analysis of crosstalk in scaled CMOS interconnects

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    The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in system

    A 200-MHz fully-differential CMOS front-end with an on-chip inductor for magnetic resonance imaging

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    Recently, there is a growing interest in applying electronic circuit design for biomedical applications, especially in the area of nuclear magnetic resonance (NMR). NMR has been used for many years as a spectroscopy technique for analytical chem- istry. Previous studies have demonstrated the design and fabrication of planar spiral inductors (microcoils) that serve as detectors for nuclear magnetic resonance mi- crospectroscopy. The goal of this research was to analyze, design, and test a prototype integrated sensor, which consisted of a similar microcoil detector with analog components to form a multiple-channel front-end for a magnetic resonance imaging (MRI) system to perform microspectroscopy. The research has succeeded in producing good function- ality for a multiple-channel sensor. The sensor met expectations compared to similar one-channel systems through experiments in channel separation and good signal-to- noise ratios

    On-chip ultra-fast data acquisition system for optical scanning acoustic microscopy using 0.35um CMOS technology

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    Optical Scanning Acoustic Microscopy (OSAM) is a non-contacting method of investigating the properties and hidden faults of solid materials. This thesis presents an ultra-fast data acquisition system (DAQ) which samples and digitises the output signal of OSAM. The author's work includes the design of the clock source and the sampler, and integration of the whole system. The clock source is a unique pulse generator based on a 2.624GHz PLL with a Quadrature VCO (QVCO), which is able to generate 4 clock signals in accurate quadrature phase difference. The pulse generator used the 4-phase clocks to provide control pulses to the sampler. The pulses were carefully aligned to the clock edges by digital logic, so that jitters were reduced as much as possible. The required short time delay for the sampler was also provided by the pulse generator, and this was implemented by a smartly-controlled switch box which re-shuffles the 4-phase clocks. The presented sampler is a novel 10.496GSample/s Sub-Sampling Sample-and-Hold Amplifier (SHA). The SHA sampled the input, and transformed its spectrum down to a low-frequency range so that it can be digitised. Charge-domain sampling strategy and double differential switches were both developed in this circuit to significantly improve the sampling speed. The periodicity of the system input was exploited in repetitive sampling to reduce the noise. These designed modules were integrated into a DAQ for a 2x8 sensor array. A pseudo-parallel scanning strategy was presented to minimise the power consumption, and a current-based buffer was applied to deliver the control pulses into the array. The DAQ was implemented on-chip in a low-cost 0.35um standard CMOS process. The measurement results showed that the DAQ successfully achieved a sampling rate more than 10GS/s, with a maximum output resolution of approximately 6 bits

    Modeling and characterization of on-chip interconnects, inductors and transformers

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    Ph.DNUS-SUPELEC JOINT PH.D. PROGRAMM

    On-chip ultra-fast data acquisition system for optical scanning acoustic microscopy using 0.35um CMOS technology

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    Optical Scanning Acoustic Microscopy (OSAM) is a non-contacting method of investigating the properties and hidden faults of solid materials. This thesis presents an ultra-fast data acquisition system (DAQ) which samples and digitises the output signal of OSAM. The author's work includes the design of the clock source and the sampler, and integration of the whole system. The clock source is a unique pulse generator based on a 2.624GHz PLL with a Quadrature VCO (QVCO), which is able to generate 4 clock signals in accurate quadrature phase difference. The pulse generator used the 4-phase clocks to provide control pulses to the sampler. The pulses were carefully aligned to the clock edges by digital logic, so that jitters were reduced as much as possible. The required short time delay for the sampler was also provided by the pulse generator, and this was implemented by a smartly-controlled switch box which re-shuffles the 4-phase clocks. The presented sampler is a novel 10.496GSample/s Sub-Sampling Sample-and-Hold Amplifier (SHA). The SHA sampled the input, and transformed its spectrum down to a low-frequency range so that it can be digitised. Charge-domain sampling strategy and double differential switches were both developed in this circuit to significantly improve the sampling speed. The periodicity of the system input was exploited in repetitive sampling to reduce the noise. These designed modules were integrated into a DAQ for a 2x8 sensor array. A pseudo-parallel scanning strategy was presented to minimise the power consumption, and a current-based buffer was applied to deliver the control pulses into the array. The DAQ was implemented on-chip in a low-cost 0.35um standard CMOS process. The measurement results showed that the DAQ successfully achieved a sampling rate more than 10GS/s, with a maximum output resolution of approximately 6 bits

    Microelectronic Design with Integrated Magnetic and Piezoelectric Structures

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    This thesis investigates the possibility of integrating the standard CMOS design process with additional microstructures enhancing circuit functionalities. More specifically, the thesis faces the problem of miniaturization of magnetic and piezoelectric devices mostly focused on the application field of EH (Energy Harvesting) systems and ultra-low power and ultra-low voltage systems. It shows all the most critical aspects which have to be taken into account during the design process of miniaturized inductors for PwrSoC (Power System on Chip) or transformers. Furthermore it shows that it is possible to optimize the inductance value and also performances by means of a proper choice of the size of the planar core or choosing a different layout shape such as a serpentine shape in place of the classic toroidal one. A new formula for the correct evaluation of the MPL (Magnetic Path Length) was also introduced. Concerning the piezoelectric counterpart, it is focused on the design and simulation of various MEMS PTs based on a SOI (Silicon on Insulator) structure with AlN (Alluminum Nitride) as active piezoelectric element, in perspective of having a SoC with embedded MEMS devices and circuitry. Furthermore it demonstrates for the first time the use of a PT (Piezoelectric Transformer) for ultra-low voltage EH applications. A new boost oscillator based on a discrete PZT (Lead Zirconate Titanate) PT instead of a MT (Magnetic Transformer) has been modelled and tested on a circuit made up by discrete devices, showing performances comparable to commercial solutions like the LTC3108 from Linear. Furthermore this novel boost oscillator has been designed in a 0.35μm technology by ST Microelectronics, showing better performances as intuitively expected by the developed mathematical model of the entire system

    Design and simulation of micro resonator oscillator for communication circuits

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    In this theses design and simulation of a Micro Electro Mechanical System (MEMS) based oscillator is presented. Electrostatic comb drive is chosen as the core structure in oscillator. MicroElectroMechanical (MEM) vibrating structures such as linear drive resonators can be used as driving components in signal processing applications. The choice of these components is assisted by the fact that these MEM devices display high quality factor values when operated under vacuum. The design of a highly stable oscillator is an example utilizing the linear drive resonators and working samples are demonstrated at 16.5 kHz. For this oscillator to be used in portable communication devices, the operating frequency will have to be increased to at least IF band (> 450kHz). MEMS based microstructures are simulated and prepared for implementation by properly adjusting the physical dimensions of the micromechanical resonator. The Dimensions of the resonator is tuned to achieve higher resonance frequencies. Electrical model and governing equations of interdigitated finger structure are studied. Based on results of these studies a micromechanical oscillator is designed to attain above-mentioned frequency. The study is carried out both analytically and on the equivalent circuit. Integration of MEMS structure with Complementary Metal Oxide Semiconductor (CMOS) electronics is another motivation and driving force of this study. Therefore completely monolithic high-Q micromechanical oscillator integrated with CMOS circuits is aimed and described. As it has high Q (over 80.000) and very stable, laterally driven microresonators can be a good miniaturized replacement of a crystal and surface acoustic wave (SAW) resonator based oscillators used in telecommunication applications. The electrical model of the microresonator is given and used as a frequency selective network in the oscillator design. Different oscillator circuits are designed and simulated to estimate and compare their performance to other mechanical based oscillators (SAW, FBAR, Crystal etc.). Analog CMOS integraated circuits are designed and optimized to achieve highly stable oscillations

    High Performance Integrated Circuit Blocks for High-IF Wideband Receivers

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    Due to the demand for high‐performance radio frequency (RF) integrated circuit design in the past years, a system‐on‐chip (SoC) that enables integration of analog and digital parts on the same die has become the trend of the microelectronics industry. As a result, a major requirement of the next generation of wireless devices is to support multiple standards in the same chip‐set. This would enable a single device to support multiple peripheral applications and services. Based on the aforementioned, the traditional superheterodyne front‐end architecture is not suitable for such applications as it would require a complete receiver for each standard to be supported. A more attractive alternative is the highintermediate frequency (IF) radio architecture. In this case the signal is digitalized at an intermediate frequency such as 200MHz. As a consequence, the baseband operations, such as down‐conversion and channel filtering, become more power and area efficient in the digital domain. Such architecture releases the specifications for most of the front‐end building blocks, but the linearity and dynamic range of the ADC become the bottlenecks in this system. The requirements of large bandwidth, high frequency and enough resolution make such ADC very difficult to realize. Many ADC architectures were analyzed and Continuous‐Time Bandpass Sigma‐Delta (CT‐BP‐ΣΔ) architecture was found to be the most suitable solution in the high‐IF receiver architecture since they combine oversampling and noise shaping to get fairly high resolution in a limited bandwidth. A major issue in continuous‐time networks is the lack of accuracy due to powervoltage‐ temperature (PVT) tolerances that lead to over 20% pole variations compared to their discrete‐time counterparts. An optimally tuned BP ΣΔ ADC requires correcting for center frequency deviations, excess loop delay, and DAC coefficients. Due to these undesirable effects, a calibration algorithm is necessary to compensate for these variations in order to achieve high SNR requirements as technology shrinks. In this work, a novel linearization technique for a Wideband Low‐Noise Amplifier (LNA) targeted for a frequency range of 3‐7GHz is presented. Post‐layout simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm, respectively. The power consumption of the LNA is 5.8mA from 2V. Secondly, the design of a CMOS 6th order CT BP‐ΣΔ modulator running at 800 MHz for High‐IF conversion of 10MHz bandwidth signals at 200 MHz is presented. A novel transconductance amplifier has been developed to achieve high linearity and high dynamic range at high frequencies. A 2‐bit quantizer with offset cancellation is alsopresented. The sixth‐order modulator is implemented using 0.18 um TSMC standard analog CMOS technology. Post‐layout simulations in cadence demonstrate that the modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth. The modulator’s static power consumption is 107mW from a supply power of ± 0.9V. Finally, a calibration technique for the optimization of the Noise Transfer Function CT BP ΣΔ modulators is presented. The proposed technique employs two test tones applied at the input of the quantizer to evaluate the noise transfer function of the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed‐mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal‐to‐Quantization Noise Ratio (SQNR) performance is extracted via Least‐ Mean Squared (LMS) software‐based algorithm. Since the two tones are located outside the band of interest, the proposed global calibration approach can be used online with no significant effect on the in‐band content

    5 GHz Optical Front End in 0.35um CMOS

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    With the advantages of low cost, low power consumption, high reliability and potential for large scale integration, CMOS monolithically integrated active pixel chips have significant application in optical sensing systems. The optical front end presented in this thesis will have application in Optical Scanning Acoustic Microscope System (O-SAM), which involves a totally non-contact method of acquiring images of the interaction between surface acoustic waves (SAWs) and a solid material to be characterized. In this work, an ultra fast optical front-end using improved regulated cascade scheme is developed based on AMS 0.35mm CMOS technology. The receiver consists of an integrated photodiode, a transimpedance amplifier, a mixer, an IF amplifier and an output buffer. By treating the n-well in standard CMOS technology as a screening terminal to block the slow photo-generated bulk carriers and interdigitizing shallow p+ junctions as the active region, the integrated photodiode operates up to 4.9 GHz with no process modification. Its responsivity was measured to be 0.016 A/W. With multi-inductive-series peaking technique, the improved ReGulated-Cascade (RGC) transimpedance amplifier achieves an experimentally measured -3dB bandwidth of more than 6 GHz and a transimpedance gain of 51 dBW, which is the fastest reported TIA in CMOS 0.35mm technology. The 5 GHz Gilbert cell mixer produces a conversion gain of 11 dB, which greatly minimized the noise contribution from the IF stage. The noise figure and input IIP3 of the mixer were measured to be 15.7 dB and 1.5 dBm, respectively. The IF amplifier and output buffer pick up and further amplify the signal for post processing. The optical front end demonstrates a typical equivalent input noise current of 35 pA=pHz at 5 GHz, and a total transimpedance gain of 83 dB ohm whileconsuming a total current of 40 mA from 3.3 V power supply. The -3 dB bandwidth for the optical front end was measured to be 4.9 GHz. All the prototype chips, including the optical front end, and the individual circuits including the photodiode, TIA, mixer were probe-tested and all the measurements were taken with Anritsu VNA 37397D and Anritsu spectrum analyser MS2721A
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