A Survey of Digital Systems Curriculum and Pedagogy in Electrical and Computer Engineering Programs

Digital Systems is one of the basic foundational courses in Electrical and Computer Engineering. One of the challenges in designing and modifying the curriculum for the course is the fast pace of technology change in the area. TTL chips that were in vogue with students building physical circuits, have given way to new paradigms like FPGA based synthesis with hardware description languages such as VHDL. However, updating a course is not as simple as just changing the book, and changing the syllabus. A large amount of work needs to be done in terms of selecting the book that will accommodate the course, the device that should be used, the laboratory content, and even how much time needs to be dedicated for every topic. All these issues, and many more makes it hard to take the decision of updating the course. For that reason, this paper surveys the pedagogy and methodology that is used to teach the digital systems curriculum at different universities. The goal is that it will serve as a resource for faculty looking to update or revamp their digital systems curricula. Within the document they will find a comparative study by electrical and computer engineering program, a list of textbooks, and the devices most commonly used.Cockrell School of Engineerin

A direct-sequence spread-spectrum communication system for integrated sensor microsystems

Some of the most important challenges in health-care technologies have been identified to be development of noninvasive systems and miniaturization. In developing the core technologies, progress is required in pushing the limits of miniaturization, minimizing the costs and power consumption of microsystems components, developing mobile/wireless communication infrastructures and computing technologies that are reliable. The implementation of such miniaturized systems has become feasible by the advent of system-on-chip technology, which enables us to integrate most of the components of a system on to a single chip. One of the most important tasks in such a system is to convey information reliably on a multiple-access-based environment. When considering the design of telecommunication system for such a network, the receiver is the key performance critical block. The paper describes the application environment, the choice of the communication protocol, the implementation of the transmitter and receiver circuitry, and research work carried out on studying the impact of input data characteristics and internal data path complexity on area and power performance of the receiver. We provide results using a test data recorded from a pH sensor. The results demonstrate satisfying functionality, area, and power constraints even when a degree of programmability is incorporated in the system

Gen-acceleration: Pioneering work for hardware accelerator generation using large language models

Optimizing computational power is critical in the age of data-intensive applications and Artificial Intelligence (AI)/Machine Learning (ML). While facing challenging bottlenecks, conventional Von-Neumann architecture with implementing such huge tasks looks seemingly impossible. Hardware Accelerators are critical in efficiently deploying these technologies and have been vastly explored in edge devices. This study explores a state-of-the-art hardware accelerator; Gemmini is studied; we leveraged the open-sourced tool. Furthermore, we developed a Hardware Accelerator in the study we compared with the Non-Von-Neumann architecture. Gemmini is renowned for efficient matrix multiplication, but configuring it for specific tasks requires manual effort and expertise. We propose implementing it by reducing manual intervention and domain expertise, making it easy to develop and deploy hardware accelerators that are time-consuming and need expertise in the field; by leveraging the Large Language Models (LLMs), they enable data-informed decision-making, enhancing performance. This work introduces an innovative method for hardware accelerator generation by undertaking the Gemmini to generate optimizing hardware accelerators for AI/ML applications and paving the way for automation and customization in the field

An FPGA based Efficient Fruit Recognition System Using Minimum Distance Classifier

The paper deals with a simple yet effective fruit identification system developed on an FPGA, SPARTAN 3(XC3S200-5PQ208) platform .The fruits under consideration were apple, banana, sapodilla and strawberry. Out of these selected fruits there were four different classes of apples, two different classes of sapodillas and one class each of the other two fruits. A total of 800 color images, 200 images of each fruit of size 64x64 were used for training. The fruit identification success rate mainly depends on the feature vector and the Classifier used. The 3D feature vector incorporates two first order statistical features and the shape feature. Using the 3D feature vector the MATLAB analysis of The Minimum Distance Classifier (MID) fetched a success rate of 85%.The Verilog coded Hardware platform was developed by burning the COE file of a Test image generated by JAVA ECLIPSE IDE onto the IP core. The MATLAB results were verified using the Hardware Platform. Keywords: RGB image, feature vector, MID, Verilog, FPGA, IP core, COE file

Effectiveness of Using MyFPGA Platform for Teaching Digital Logic

Accompanying electric circuits and computer programming, digital logic is deemed one of the most essential parts of any Electrical and Computer Engineering curriculum, so student success in the course is critical. Furthermore, research shows that the academic performance of students is heavily dependent upon student engagement, which is believed to increase with classroom strategies such as flipped-classrooms, cooperative learning, project-based learning, and virtual labs. The University of Texas Rio Grande Valley (UTRGV) is a Hispanic serving institution with distributive campuses, where many of the students work part-time. With consideration of the special needs of our students and the latest developments in engineering education, this study focuses on our recent experience of teaching digital logical using MyFPGA, online FPGA platform. We first introduce the MyFPGA platform in this paper. Developed by one of the authors of this paper, this web-based design features I/O interfacing circuits with an Intel FPGA hardware board as well as API web services with the Intel Quartus II design software. The platform provides 24/7 real-time hardware design experience at students’ fingertips, requiring only a web browser and internet access. It exposes the students to a complete engineering design cycle that includes problem specification, block diagram design, HDL source code design, simulation and hardware verification, trouble shooting and evaluation, and reporting. We consider different cases of the platform usage in two digital logic courses. To evaluate the effectiveness of the student learning experience, data is collected using outcome assessments, student feedback and self-evaluations, instructor observations, and comparative studies. Preliminary results confirmed the effectiveness of the online digital design platform. We have also identified a few pitfalls, such as instructors’ initial reluctance in adopting the platform and students’ first perception of the platform as a pure simulation tool. Based on the studies, recommendations are made to identify the best practices in the utilization of the platform to better serve Electrical and Computer Engineering majors and secondary school students interested in the general STEM fields

Experiential Learning in Computer Engineering using Basic Logic Design Circuits

Abstract- One of the main tracks of research is about Low-cost computing devices in engineering educations. This track face the problem that conventual methods are either too trivial demonstrative educational examples, or too abstracted that it hides away the necessary details students should learn, or too complex industry grade demonstrations. This research targets to utilize lost cost computing devices, and produce multiple step-by-step, educational components for university level. It relies on on the experiential learning methodology via generating multiple level educational components for Field Programmable Gate Array (FPGA) devices. Two basic design circuits were illustrated in this paper for two different FPGA boards, A comparison between conventional methods and proposed methods is also presented showing a favorable benefit, thus we disseminate this technique to researchers universities in the nation and abroad.A comparison between conventional methods and proposed methods is also presented showing a favorable benefit, thus we disseminate this technique to researchers universities in the nation and abroad

Theoretical Design and FPGA-Based Implementation of Higher-Dimensional Digital Chaotic Systems

Traditionally, chaotic systems are built on the domain of infinite precision in mathematics. However, the quantization is inevitable for any digital devices, which causes dynamical degradation. To cope with this problem, many methods were proposed, such as perturbing chaotic states and cascading multiple chaotic systems. This paper aims at developing a novel methodology to design the higher-dimensional digital chaotic systems (HDDCS) in the domain of finite precision. The proposed system is based on the chaos generation strategy controlled by random sequences. It is proven to satisfy the Devaney's definition of chaos. Also, we calculate the Lyapunov exponents for HDDCS. The application of HDDCS in image encryption is demonstrated via FPGA platform. As each operation of HDDCS is executed in the same fixed precision, no quantization loss occurs. Therefore, it provides a perfect solution to the dynamical degradation of digital chaos.Comment: 12 page