195 research outputs found

    Optical Interconnect Waveguide in Electronic Circuit

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    The increasing demand in silicon nano-photonics has encouraged many researchers to put more efforts to explore the feasibility of using optics in the communication medium in order to replace the conventional electrical interconnects (EIs). In this paper, we proposed a SOI- based waveguide in the optical interconnect (OI) link at an operating frequency of 1550nm to work as an interconnection path in a circuit. The performance capability of the OI link was tested using a two-stage CE amplifier to work as the interconnection path from the 1st stage to the 2nd stage amplifier. In term of optical performances, the optical waveguide interconnect managed to achieve a single mode condition for a TE mode and fulfill the receiver sensitivity of a photodiode. While, in term of electrical performance, a two-stage CE amplifier is able to produce a high gain, a wide bandwidth and high slew rate. The proposed implementation of the OIs waveguide is succesfully enhance the performance of the two-stage CE amplifier as well as the analog electronic circuit applications

    Circuit paradigm in the 21

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    On-Chip Optical Interconnection Networks for Multi/Manycore Architectures

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    The rapid development of multi/manycore technologies offers the opportunity for highly parallel architectures implemented on a single chip. While the first, low-parallelism multicore products have been based on simple interconnection structures (single bus, very simple crossbar), the emerging highly parallel architectures will require complex, limited-degree interconnection networks. This thesis studies this trend according to the general theory of interconnection structures for parallel machines, and investigates some solutions in terms of performance, cost, fault-tolerance, and run-time support to shared-memory and/or message passing programming mechanisms

    Cutting Edge Nanotechnology

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    The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters

    Multifunctional vertical interconnections of multilayered flexible substrates for miniaturised POCT devices

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    Point-of-care testing (POCT) is an emerging technology which can lead to an eruptive change of lifestyle and medication of population against the traditional medical laboratory. Since living organisms are intrinsically flexible and malleable, the flexible substrate is a necessity for successful integration of electronics in biological systems that do not cause discomfort during prolonged use. Isotropic conductive adhesives (ICAs) are attractive to wearable POCT devices because ICAs are environmentally friendly and allow a lower processing temperature than soldering which protects heat-sensitive components. Vertical interconnections and optical interconnections are considered as the technologies to realise the miniaturised high-performance devices for the future applications. This thesis focused on the multifunctional integration to enable both electrical and optical vertical interconnections through one via hole that can be fabricated in flexible substrates. The functional properties of the via and their response to the external loadings which are likely encountered in the POCT devices are the primary concerns of this PhD project. In this thesis, the research of curing effect on via performance was first conducted by studying the relationship between curing conditions and material properties. Based on differential scanning calorimetry (DSC) analysis results, two-parameter autocatalytic model (Sestak-Berggren model) was established as the most suitable curing process description of our typical ICA composed of epoxy-based binders and Ag filler particles. A link between curing conditions and the mechanical properties of ICAs was established based on the DMA experiments. A series of test vehicles containing vias filled with ICAs were cured under varying conditions. The electrical resistance of the ICA filled vias were measured before testing and in real time during thermal cycling tests, damp heat tests and bending tests. A simplified model was derived to represent rivet-shaped vias in the flexible printed circuit boards (FPCBs) based on the assumption of homogenous ICAs. An equation was thus proposed to evaluate the resistance of the model. Vias with different cap sizes were also tested, and the equation was validated. Those samples were divided into three groups for thermal cycling test, damp heat ageing test and bending test. Finite element analysis (FEA) was used to aid better understanding of the electrical conduction mechanisms. Based on theoretical equation and simulation model, the fistula-shape ICA via was fabricated in flexible PCB. Its hollow nature provides the space for integrations of optical or fluidic circuits. Resistance measurements and reliability tests proved that carefully designed and manufactured small bores in vias did not comprise the performance. Test vehicles with optoelectrical vias were made through two different approaches to prove the feasibility of multifunctional vertical interconnections in flexible substrates. A case study was carried out on reflection Photoplethysmography (rPPG) sensors manufacturing, using a specially designed optoelectronic system. ICA-based low-temperature manufacture processes were developed to enable the integration of these flexible but delicate substrates and components. In the manufacturing routes, a modified stencil printing setup, which merges two printing-curing steps (vias forming and components bonding) into one step, was developed to save both time and energy. The assembled probes showed the outstanding performance in functional and physiological tests. The results from this thesis are anticipated to facilitate the understanding of ICA via conduction mechanism and provide an applicable tool to optimise the design and manufacturing of optoelectrical vias

    Towards an on-chip power supply: Integration of micro energy harvesting and storage techniques for wireless sensor networks

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    The lifetime of a power supply in a sensor node of a wireless sensor network is the decisive factor in the longevity of the system. Traditional Li-ion batteries cannot fulfill the demands of sensor networks that require a long operational duration. Thus, we require a solution that produces its own electricity from its surrounding and stores it for future utility. Moreover, as the sensor node architecture is developed on complimentary metal-oxide-semiconductor technology (CMOS), the manufacture of the power supply must be compatible with it. In this thesis, we shall describe the components of an on-chip lifetime power supply that can harvest the vibrational mechanical energy through piezoelectric microcantilevers and store it in a reduced graphene oxide (rGO) based microsupercapacitor, and that is fabricated through CMOS compatible techniques. Our piezoelectric microcantilevers confirm the feasibility of fabricating micro electro- mechanical-systems (MEMS) size two-degree-of-freedom systems which can solve the major issue of small bandwidth of piezoelectric micro-energy harvesters. These devices use a cut-out trapezoidal cantilever beam to enhance the stress on the cantilever’s free end while reducing the gap remarkably between its first two eigenfrequencies in 400 - 500 Hz and 1 - 2 kHz range. The energy from the M-shaped harvesters will be stored in rGO based microsupercapacitors. These microsupercapacitors are manufactured through a fully CMOS compatible, reproducible, and reliable micromachining processes. Furthermore, we have also demonstrated an improvement in their electrochemical performance and yield of fabrication through surface roughening from iron nanoparticles. We have also examined the possibility of integrating these devices into a power management unit to fully realize a lifetime power supply for wireless sensor networks

    A novel low-swing voltage driver design and the analysis of its robustness to the effects of process variation and external disturbances

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    arket forces are continually demanding devices with increased functionality/unit area; these demands have been satisfied through aggressive technology scaling which, unfortunately, has impacted adversely on the global interconnect delay subsequently reducing system performance. Line drivers have been used to mitigate the problems with delay; however, these have a large power consumption. A solution to reducing the power dissipation of the drivers is to use lower supply voltages. However, by adopting a lower power supply voltage, the performance of the line drivers for global interconnects is impaired unless low-swing signalling techniques are implemented. Low-swing signalling techniques can provide high speed signalling with low power consumption and hence can be used to drive global on-chip interconnect. Most of the proposed low-swing signalling schemes are immune to noise as they have a good SNR. However, they tend to have a large penalty in area and complexity as they require additional circuitry such as voltage generators and low-Vth devices. Most of the schemes also incorporate multiple Vdd and reference voltages which increase the overall circuit complexity. A diode-connected driver circuit has the best attributes over other low-swing signalling techniques in terms of low power, low delay, good SNR and low area overhead. By incorporating a diode-connected configuration at the output, it can provide high speed signalling due to its high driving capability. However, this configuration also has its limitations as it has issues with its adaptability to process variations, as well as an issue with leakage currents. To address these limitations, two novel driver schemes have been designed, namely, nLVSD and mLVSD, which, additionally, have improvements in performance and power consumption. Comparisons between the proposed schemes with the existing diode-connected driver circuits (MJ and DDC) showed that the nLVSD and mLVSD drivers have approximately 46% and 50% less delay. The name MJ originates from the driver’s designer called Juan A. Montiel-Nelson, while DDC stands for dynamic diode-connected. In terms of power consumption, the nLVSD and mLVSD drivers also produce 43% and 7% improvement. Additionally, the mLVSD driver scheme is the most robust as its SNR is 14 to 44% higher compared to other diode-connected driver circuits. On the other hand, the nLVSD driver has 6% lower SNR compared to the MJ driver, even though it is 19% more robust than the DDC driver. However, since its SNR is still above 1, its improved performance and reduced power consumption, as well other advantages it has over other diode-connected driver circuits can compensate for this limitation. Regarding the robustness to external disturbances, the proposedmdriver circuits are more robust to crosstalk effects as the nLVSD and mLVSD drivers are approximately 35% and 7% more robust than other diode-connected drivers. Furthermore, the mLVSD driver is 5%, 33% and 47% more tolerant to SEUs compared to the nLVSD, MJ and DDC driver circuits respectively, whilst the MJ and DDC drivers are 26% and 40% less tolerant to SEUs iii compared to the nLVSD circuit. A comparison between the four schemes was also undertaken in the presence of ±3σ process and voltage (PV) variations. The analysis indicated that both proposed driver schemes are more robust than other diode-connected driver schemes, namely, the MJ and DDC driver circuits. The MJ driver scheme deviates approximately 18% and 35% more in delay and power consumption compared to the proposed schemes. The DDC driver has approximately 20% and 57% more variations in delay and power consumption in comparison to the proposed schemes. In order to further improve the robustness of the proposed driver circuits against process variation and environmental disturbances, they were further analysed to identify which process variables had the most impact on circuit delay and power consumption, as well as identifying several design techniques to mitigate problems with environmental disturbances. The most significant process parameters to have impact on circuit delay and power consumption were identified to be Vdd, tox, Vth, s, w and t. The impact of SEUs on the circuit can be reduced by increasing the bias currents whilst design methods such as increasing the interconnect spacing can help improve the circuit robustness against crosstalk. Overall it is considered that the proposed nLVSD and mLVSD circuits advance the state of the art in driver design for on-chip signalling applications.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

    Caractérisation et modélisation d'interconnexions. Développement de nouvelles solutions pour la transmission d'informations au sein des cartes et puces électroniques.

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    Since the first IC in 1959 the performances and computing capacity of electronic devices have always grown, following thus the well-known empirical Moore’s law which says that the number of transistors in a dense integrated circuit doubles approximately every 18 months. This prevision is still verified even if some limitations appears like for example the limitation of the clock frequency which grow less than the projection that the ITRS (International Technology Roadmap for Semiconductors) has made in 2000. One of the stumbling point comes from interconnects which ensure the transmission of information inside electronic chips or cards. The interconnects imply delay, signal distortion, crosstalk and power dissipation and they now must be taken into account during electronic device design. So the researches depicted in this manuscript deal with the modelling of interconnect and study of new solutions to overcome problems due to classical interconnects. These works have been realized in Lab-STICC laboratory with the help of colleagues, post-doc, PhDs and Master Students. The manuscript include three chapters, the first one concerns researches on modelling aspects, the second is about alternative solutions to classical wired interconnects and to conclude the research projects for the next years are presented.The first chapter concern researches about modelling which aim to develop reliable models in view to simulate more quickly the electrical behavior of interconnects. Firstly the collaborations concerning the development of model-order reduction are presented. Then with the aim to evaluate the impact of inductive behavior, the current return patch problem and so the extraction of loop inductance is treated. The 3D discontinuities and 3D environment effects are presented in the third part of this chapter. For example the parallel grid influences on propagation are explored as well as the case of coupling between microvias and parallel-plates cavities inside multilayer PCB.The second chapter is about research of new solutions to overcome the limitation due to classical wired interconnects. A review of envisaged alternative solutions like for example optical interconnects and CNT (carbon Nano Tube) is first presented. Then a focus on RF guided interconnect is made and constraints in term of bandwidth are explained and some coupling techniques are explored. These studies naturally lead to exploration of the paradigm of wireless interconnects and the preliminary researches on radio transmission between two circuits placed on a PCB are shown. All these approaches of RF wireless interconnect are prelude to the research projects which are developed in a third chapter of the manuscript.The development of the draft over 4 years is based on the BBC project (wireless interconnect network on chip or in board for Broadcast-Based parallel Computing) funded by the Labex COMINLABS and which will begin in October 2016. The aims of this project are outlined as well as the aims of another project entitled “BROADWAYS” (Broadcast-Based new paradigms of ubiquitous memory mapping, bandwidth allocation and parallel programing made possible by Radio Network On Chip) which is currently in the second step of review by the ANR. To conclude this research part other embryonic researches are presented as well as long term researches envisaged like terahertz applications of the use of graphene for microwave applications.Depuis les premiers circuits intĂ©grĂ©s en 1959 les composants et les systĂšmes Ă©lectroniques n’ont cessĂ© de voir leurs performances augmenter suivant ainsi la loi empirique de Gordon Moore qui prĂ©voit un doublement de la complexitĂ© des circuits tous les 18 mois. Cette prĂ©vision reste aujourd’hui toujours vĂ©rifiĂ©e mĂȘme si nous constatons depuis une dizaine d’annĂ©es que les frĂ©quences d’horloges stagnent autour de 4-5 GHz alors que l’ITRS (International Technology Roadmap for Semiconductors) prĂ©voyait dans les annĂ©es 2000 des frĂ©quences de travail pouvant atteindre 40 GHz pour 2016. L’un des facteurs limitant la progression des performances vient des interconnexions mĂ©talliques servant au transport de l’information au sein des systĂšmes Ă©lectroniques. Les travaux de recherche prĂ©sentĂ©s dans le cadre de l’obtention de l‘habilitation Ă  diriger des recherches concernent d’une part les travaux rĂ©alisĂ©s sur la modĂ©lisation des interconnexions et d’autre part ceux sur l’étude de solutions alternatives Ă  ces interconnexions classiques. Ces travaux ont Ă©tĂ© rĂ©alisĂ©s au sein du Lab-STICC en collaboration avec plusieurs collĂšgues et lors de l’encadrement de plusieurs post-doctorants, doctorants et stagiaires de master recherche. Le mĂ©moire comporte trois chapitres principaux, le premier concerne les travaux sur la modĂ©lisation des interconnexions, le second porte sur l’étude de solutions alternatives Ă  ces interconnexions classiques et le dernier permet la prĂ©sentation des projets de recherches pour les prochaines annĂ©es.L’objectif de nos travaux sur la modĂ©lisation des interconnexions consiste au dĂ©veloppement de modĂšles fiables permettant d’apprĂ©hender leurs effets sur les signaux. Dans un premier temps, les travaux portant sur l’obtention de modĂšles Ă  complexitĂ© rĂ©duite sont prĂ©sentĂ©s. Puis, afin d’évaluer l’impact des effets inductifs des interconnexions, nous prĂ©sentons les travaux sur l’identification des chemins de retours du courant dans un rĂ©seau comprenant plusieurs lignes et qui sont nĂ©cessaires pour dĂ©terminer les inductances de boucles. La prise en compte de l’environnement 3D des interconnexions fait l’objet de la troisiĂšme partie de ce chapitre. Nous traitons ainsi de l’influence de diffĂ©rentes discontinuitĂ©s et nous prĂ©sentons des rĂšgles de design permettant la limitation des risques de conversion de mode de propagation. Dans le cadre de structures multicouches, nous abordons l’influence de grilles mĂ©talliques placĂ©es au voisinage d’une ligne sur la propagation des signaux. Enfin nous traitons des risques de couplage entre des vias et les modes de cavitĂ©s au sein des structures PCB multicouches.La seconde thĂ©matique dĂ©veloppĂ©e dans ce mĂ©moire porte sur le dĂ©veloppement de solutions alternatives aux interconnexions classiques. AprĂšs avoir listĂ© certaines de ces solutions telle que les interconnexions optiques ou les nanotubes de carbone, nous prĂ©sentons plus particuliĂšrement les interconnexions RF qui vĂ©hiculent l’information numĂ©rique sur porteuse Ă  haute frĂ©quence. Dans un premier temps nous analysons les interconnexions RF guidĂ©es qui utilisent une ligne de transmission comme support pour transporter l’information. A partir de l’étude des modes d’accĂšs multiples nous montrons que les canaux doivent ĂȘtre large bande et nous explorons diverses façons de transmettre l’énergie Ă  la ligne de transmission. Enfin nous prĂ©sentons quelques exemples de performances obtenues Ă  l’aide de dĂ©monstrateurs numĂ©riques. Ces Ă©tudes des interconnexions RF guidĂ©es nous ont naturellement amenĂ© Ă  considĂ©rer les possibilitĂ©s de transmission par voie hertzienne des informations au sein des cartes et puces Ă©lectroniques. Nous avons ainsi analysĂ© Ă  l’aide de dĂ©monstrateurs trĂšs simples les niveaux de transmission entre deux circuits placĂ©s sur une mĂȘme carte PCB (Printed Circuit Board).Ces Ă©tudes initiales sur les interconnexions radios ou sans fils servent de point d’appui aux projets de recherche prĂ©sentĂ©s Ă  la fin de ce manuscrit. La philosophie du projet BBC (wireless interconnect network on chip or in board for Broadcast-Based parallel Computing) financĂ© par le Labex COMINLABS Ă  partir d’octobre est prĂ©sentĂ© de mĂȘme que celle du projet ANR Broadways (Broadcast-Based new paradigms of ubiquitous memory mapping, bandwidth allocation and parallel programing made possible by Radio Network On Chip) en seconde phase d’étude auprĂšs de l’ANR

    Miniaturized Transistors, Volume II

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    In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before
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