On Compact Routing for the Internet

While there exist compact routing schemes designed for grids, trees, and Internet-like topologies that offer routing tables of sizes that scale logarithmically with the network size, we demonstrate in this paper that in view of recent results in compact routing research, such logarithmic scaling on Internet-like topologies is fundamentally impossible in the presence of topology dynamics or topology-independent (flat) addressing. We use analytic arguments to show that the number of routing control messages per topology change cannot scale better than linearly on Internet-like topologies. We also employ simulations to confirm that logarithmic routing table size scaling gets broken by topology-independent addressing, a cornerstone of popular locator-identifier split proposals aiming at improving routing scaling in the presence of network topology dynamics or host mobility. These pessimistic findings lead us to the conclusion that a fundamental re-examination of assumptions behind routing models and abstractions is needed in order to find a routing architecture that would be able to scale ``indefinitely.''Comment: This is a significantly revised, journal version of cs/050802

On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175

Neighbor selection and hitting probability in small-world graphs

Small-world graphs, which combine randomized and structured elements, are seen as prevalent in nature. Jon Kleinberg showed that in some graphs of this type it is possible to route, or navigate, between vertices in few steps even with very little knowledge of the graph itself. In an attempt to understand how such graphs arise we introduce a different criterion for graphs to be navigable in this sense, relating the neighbor selection of a vertex to the hitting probability of routed walks. In several models starting from both discrete and continuous settings, this can be shown to lead to graphs with the desired properties. It also leads directly to an evolutionary model for the creation of similar graphs by the stepwise rewiring of the edges, and we conjecture, supported by simulations, that these too are navigable.Comment: Published in at http://dx.doi.org/10.1214/07-AAP499 the Annals of Applied Probability (http://www.imstat.org/aap/) by the Institute of Mathematical Statistics (http://www.imstat.org

Compact Routing on Internet-Like Graphs

The Thorup-Zwick (TZ) routing scheme is the first generic stretch-3 routing scheme delivering a nearly optimal local memory upper bound. Using both direct analysis and simulation, we calculate the stretch distribution of this routing scheme on random graphs with power-law node degree distributions, $P_k \sim k^{-\gamma}$. We find that the average stretch is very low and virtually independent of $\gamma$. In particular, for the Internet interdomain graph, $\gamma \sim 2.1$, the average stretch is around 1.1, with up to 70% of paths being shortest. As the network grows, the average stretch slowly decreases. The routing table is very small, too. It is well below its upper bounds, and its size is around 50 records for $10^4$-node networks. Furthermore, we find that both the average shortest path length (i.e. distance) $\bar{d}$ and width of the distance distribution $\sigma$ observed in the real Internet inter-AS graph have values that are very close to the minimums of the average stretch in the $\bar{d}$- and $\sigma$-directions. This leads us to the discovery of a unique critical quasi-stationary point of the average TZ stretch as a function of $\bar{d}$ and $\sigma$. The Internet distance distribution is located in a close neighborhood of this point. This observation suggests the analytical structure of the average stretch function may be an indirect indicator of some hidden optimization criteria influencing the Internet's interdomain topology evolution.Comment: 29 pages, 16 figure

Fast Routing Table Construction Using Small Messages

We describe a distributed randomized algorithm computing approximate distances and routes that approximate shortest paths. Let n denote the number of nodes in the graph, and let HD denote the hop diameter of the graph, i.e., the diameter of the graph when all edges are considered to have unit weight. Given 0 < eps <= 1/2, our algorithm runs in weak-O(n^(1/2 + eps) + HD) communication rounds using messages of O(log n) bits and guarantees a stretch of O(eps^(-1) log eps^(-1)) with high probability. This is the first distributed algorithm approximating weighted shortest paths that uses small messages and runs in weak-o(n) time (in graphs where HD in weak-o(n)). The time complexity nearly matches the lower bounds of weak-Omega(sqrt(n) + HD) in the small-messages model that hold for stateless routing (where routing decisions do not depend on the traversed path) as well as approximation of the weigthed diameter. Our scheme replaces the original identifiers of the nodes by labels of size O(log eps^(-1) log n). We show that no algorithm that keeps the original identifiers and runs for weak-o(n) rounds can achieve a polylogarithmic approximation ratio. Variations of our techniques yield a number of fast distributed approximation algorithms solving related problems using small messages. Specifically, we present algorithms that run in weak-O(n^(1/2 + eps) + HD) rounds for a given 0 < eps <= 1/2, and solve, with high probability, the following problems: - O(eps^(-1))-approximation for the Generalized Steiner Forest (the running time in this case has an additive weak-O(t^(1 + 2eps)) term, where t is the number of terminals); - O(eps^(-2))-approximation of weighted distances, using node labels of size O(eps^(-1) log n) and weak-O(n^(eps)) bits of memory per node; - O(eps^(-1))-approximation of the weighted diameter; - O(eps^(-3))-approximate shortest paths using the labels 1,...,n.Comment: 40 pages, 2 figures, extended abstract submitted to STOC'1

A procedural method for the efficient implementation of full-custom VLSI designs

An imbedded language system for the layout of very large scale integration (VLSI) circuits is examined. It is shown that through the judicious use of this system, a large variety of circuits can be designed with circuit density and performance comparable to traditional full-custom design methods, but with design costs more comparable to semi-custom design methods. The high performance of this methodology is attributable to the flexibility of procedural descriptions of VLSI layouts and to a number of automatic and semi-automatic tools within the system

On space-stretch trade-offs: upper bounds

One of the fundamental trade-offs in compact routing schemes is between the space used to store the routing table on each node and the stretch factor of the routing scheme – the maximum ratio over all pairs between the cost of the route induced by the scheme and the cost of a minimum cost path between the same pair. All previous routing schemes required storage that is dependent on the diameter of the network. We present a new scale-free routing scheme, whose storage and header sizes are independent of the aspect ratio of the network. Our scheme is based on a decomposition into sparse and dense neighborhoods. Given an undirected network with arbitrary weights and n arbitrary node names, for any integer k ≥ 1 we present the first scale-free routing scheme with asymptotically optimal space-stretch tradeoff that does not require edge weights to be polynomially bounded. The scheme uses e O(n 1/k) space routing table at each node, and routes along paths of asymptotically optimal linear stretch O(k)