Enhanced Model of Nonlinear Spiral High Voltage Divider

This paper deals with the enhanced accurate DC and RF model of nonlinear spiral polysilicon voltage divider. The high resistance polysilicon divider is a sensing part of the high voltage start-up MOSFET transistor that can operate up to 700 V. This paper presents the structure of a proposed model, implemented voltage, frequency and temperature dependency, and scalability. A special attention is paid to the ability of the created model to cover the mismatch and influence of a variation of process parameters on the device characteristics. Finally, the comparison of measured data vs. simulation is presented in order to confirm the model validity and a typical application is demonstrated

Novel Computing Paradigms using Oscillators

This dissertation is concerned with new ways of using oscillators to perform computational tasks. Specifically, it introduces methods for building finite state machines (for general-purpose Boolean computation) as well as Ising machines (for solving combinatorial optimization problems) using coupled oscillator networks.But firstly, why oscillators? Why use them for computation?An important reason is simply that oscillators are fascinating. Coupled oscillator systems often display intriguing synchronization phenomena where spontaneous patterns arise. From the synchronous flashing of fireflies to Huygens' clocks ticking in unison, from the molecular mechanism of circadian rhythms to the phase patterns in oscillatory neural circuits, the observation and study of synchronization in coupled oscillators has a long and rich history. Engineers across many disciplines have also taken inspiration from these phenomena, e.g., to design high-performance radio frequency communication circuits and optical lasers. To be able to contribute to the study of coupled oscillators and leverage them in novel paradigms of computing is without question an interesting andfulfilling quest in and of itself.Moreover, as Moore's Law nears its limits, new computing paradigms that are different from mere conventional complementary metal–oxide–semiconductor (CMOS) scaling have become an important area of exploration. One broad direction aims to improve CMOS performance using device technology such as fin field-effect transistors (FinFET) and gate-all-around (GAA) FETs. Other new computing schemes are based on non-CMOS material and device technology, e.g., graphene, carbon nanotubes, memristive devices, optical devices, etc.. Another growing trend in both academia and industry is to build digital application-specific integrated circuits (ASIC) suitable for speeding up certain computational tasks, often leveraging the parallel nature of unconventional non-von Neumann architectures. These schemes seek to circumvent the limitations posed at the device level through innovations at the system/architecture level.Our work on oscillator-based computation represents a direction that is different from the above and features several points of novelty and attractiveness. Firstly, it makes meaningful use of nonlinear dynamical phenomena to tackle well-defined computational tasks that span analog and digital domains. It also differs from conventional computational systems at the fundamental logic encoding level, using timing/phase of oscillation as opposed to voltage levels to represent logic values. These differences bring about several advantages. The change of logic encoding scheme has several device- and system-level benefits related to noise immunity and interference resistance. The use of nonlinear oscillator dynamics allows our systems to address problems difficult for conventional digital computation. Furthermore, our schemes are amenable to realizations using almost all types of oscillators, allowing a wide variety of devices from multiple physical domains to serve as the substrate for computing. This ability to leverage emerging multiphysics devices need not put off the realization of our ideas far into the future. Instead, implementations using well-established circuit technology are already both practical and attractive.This work also differs from all past work on oscillator-based computing, which mostly focuses on specialized image preprocessing tasks, such as edge detection, image segmentation and pattern recognition. Perhaps its most unique feature is that our systems use transitions between analog and digital modes of operation --- unlike other existing schemes that simply couple oscillators and let their phases settle to a continuum of values, we use a special type of injection locking to make each oscillator settle to one of the several well-defined multistable phase-locked states, which we use to encode logic values for computation. Our schemes of oscillator-based Boolean and Ising computation are built upon this digitization of phase; they expand the scope of oscillator-based computing significantly.Our ideas are built on years of past research in the modelling, simulation and analysis of oscillators. While there is a considerable amount of literature (arguably since Christiaan Huygens wrote about his observation of synchronized pendulum clocks in the 17th century) analyzing the synchronization phenomenon from different perspectives at different levels, we have been able to further develop the theory of injection locking, connecting the dots to find a path of analysis that starts from the low-level differential equations of individual oscillators and arrives at phase-based models and energy landscapes of coupled oscillator systems. This theoretical scaffolding is able not only to explain the operation of oscillator-based systems, but also to serve as the basis for simulation and design tools. Building on this, we explore the practical design of our proposed systems, demonstrate working prototypes, as well as develop the techniques, tools and methodologies essential for the process

Modeling and simulation of full-component integrated circuits in transient ESD events

This thesis presents a methodology to model and simulate transient electrostatic discharge (ESD) responses of integrated circuits (IC). To obtain valid simulation results, the IC component must be represented by a circuit netlist composed of device models that are valid under the ESD conditions. Models of the nonlinear devices that make up the ESD protection network of the IC must have transient I-V responses calibrated against measurements that emulate ESD events. Interconnects, power distribution networks, and the silicon substrate on the chip die as well as on the IC package must be faithfully constructed to emulate the fact that ESD current flows in a distributed manner across the entire IC component. The resultant equivalent circuit model therefore contains a huge number of nodes and devices, and the simulation runtime may be prohibitively long. Techniques must be devised to make the numerical simulation process more efficient without sacrifice of accuracy. These techniques include reasonable abstraction of the distributed full-component circuit netlist, dynamic piecewise-linear device models, and customized efficient transient circuit simulator. With the simulation streamlining techniques set up properly, comprehensive and predictive transient ESD simulation can be carried out efficiently to investigate the weakest link in the target IC, and the design can be fine-tuned to achieve optimal performance in both functionality and ESD reliability

Integrated Circuit Design for Hybrid Optoelectronic Interconnects

This dissertation focuses on high-speed circuit design for the integration of hybrid optoelectronic interconnects. It bridges the gap between electronic circuit design and optical device design by seamlessly incorporating the compact Verilog-A model for optical components into the SPICE-like simulation environment, such as the Cadence design tool. Optical components fabricated in the IME 130nm SOI CMOS process are characterized. Corresponding compact Verilog-A models for Mach-Zehnder modulator (MZM) device are developed. With this approach, electro-optical co-design and hybrid simulation are made possible. The developed optical models are used for analyzing the system-level specifications of an MZM based optoelectronic transceiver link. Link power budgets for NRZ, PAM-4 and PAM-8 signaling modulations are simulated at system-level. The optimal transmitter extinction ratio (ER) is derived based on the required receiver\u27s minimum optical modulation amplitude (OMA). A limiting receiver is fabricated in the IBM 130 nm CMOS process. By side- by-side wire-bonding to a commercial high-speed InGaAs/InP PIN photodiode, we demonstrate that the hybrid optoelectronic limiting receiver can achieve the bit error rate (BER) of 10-12 with a -6.7 dBm sensitivity at 4 Gb/s. A full-rate, 4-channel 29-1 length parallel PRBS is fabricated in the IBM 130 nm SiGe BiCMOS process. Together with a 10 GHz phase locked loop (PLL) designed from system architecture to transistor level design, the PRBS is demonstrated operating at more than 10 Gb/s. Lessons learned from high-speed PCB design, dealing with signal integrity issue regarding to the PCB transmission line are summarized

Enhanced modeling methodology for system-level electrostatic discharge simulation

To enable accurate system-level electrostatic discharge (ESD) simulation, models for the equipment under test, the ESD source, and the environment are required. This work presents advanced modeling methods for the ESD source, the victim IC, and other on-board components, most notably the transient voltage suppressor. Kernel regression is used to generate an enhanced quasistatic I-V model of an IC pin, which reflects its dependency on the circuit board’s power delivery network. S-parameter measurements enable the development of a model for an IEC 61000-4-2 ESD source that comprehends the coupling among the ground straps and the ground plane. The transient-voltage-suppressor device is modeled using a behavioral snapback model that shows better convergence in circuit simulation than piece-wise models. Furthermore, ESD-induced soft failures are often caused by the noise coupled between the IC package traces. To help identify this type of failure, a hybrid electromagnetic and circuit simulation approach is demonstrated

Modeling of electrical circuit with recurrent neural networks

In this dissertation, a circuit modeling methodology using recurrent neural networks (RNNs) is developed. The methodology covers model structure selection, data generation, training, and model implementation for circuit simulation. Several different RNN structures are investigated and their capabilities in circuit modeling are compared. The stability of RNN in the context of circuit modeling is defined and methods to guarantee stability for some RNN structures are developed. The modeling methodology is supported by test cases showing the accuracy and efficiency of RNN models

Analysis and modeling methods for predicting functional robustness of integrated circuits during fast transient events

La miniaturisation des circuits intégrés se poursuit de nos jours avec le développement de technologies toujours plus fines et denses. Elle permet une intégration des circuits toujours plus massive, avec des performances plus élevées et une réduction des coûts de production. La réduction de taille des circuits s'accompagne aussi d'une augmentation de leur sensibilité électrique. L'électronique automobile est un acteur majeur dans la nouvelle tendance des véhicules autonomes. Ce type d'application a besoin d'analyser des données et d'appliquer des actions sur le véhicule en temps réel. L'objectif à terme est d'améliorer la sécurité des usagers. Il est donc vital de garantir que ces modules électroniques pourront effectuer leurs tâches correctement malgré toutes les perturbations auxquelles ils seront exposés. Néanmoins, l'environnement automobile est particulièrement sévère pour l'électronique. Parmi tous les stress rencontrés, les décharges électrostatiques (ESD - Electrostatic Discharge) sont une importante source d'agression électrique. Ce type d'évènement très bref est suffisamment violent pour détruire des composants électroniques ou les perturber pendant leur fonctionnement. Les recherches présentées ici se concentrent sur l'analyse des défaillances fonctionnelles. À cause des ESD, des fonctions électroniques peuvent cesser temporairement d'être opérantes. Des méthodes d'analyse et de prédiction sont requises au niveau-circuit intégré afin de détecter des points de faiblesses susceptibles de générer des fautes fonctionnelles pendant l'exposition à un stress électrostatique. Différentes approches ont été proposées dans ce but. Une méthode hiérarchique de modélisation a été mise au point afin d'être capable de reproduire la forme d'onde ESD jusqu'à l'entrée du circuit intégré. Avec cette approche, chaque élément du système est modélisé individuellement puis son modèle ajouté au schéma complet. Un cas d'étude réaliste de défaillance fonctionnelle d'un circuit intégré a été analysé à l'aide d'outils de simulation. Afin d'obtenir plus de données sur cette faute, une puce de test a été développée, contenant des structures de surveillance et de mesure directement intégrées dans la puce. La dernière partie de ce travail de recherche est concentrée sur le développement de méthodes d'analyse dans le but d'identifier efficacement des fautes par simulation. Une des techniques développées consiste à modéliser chaque bloc d'une fonction individuellement puis permet de chaîner ces modèles afin de déterminer la robustesse de la fonction complète. La deuxième méthode tente de construire un modèle équivalent dit boite-noire d'une fonction de haut-niveau d'un circuit intégré. Ces travaux de recherche ont mené à la mise au point de prototypes matériels et logiciels et à la mise en évidence de points bloquants qui pourront constituer une base pour de futurs travaux.Miniaturization of electronic circuits continues nowadays with the more recent technology nodes being applied to diverse fields of application such as automotive. Very dense and small integrated circuits are interesting for economic reasons, because they are cheaper to manufacture in mass and can pack more functionalities with elevated performances. The counterpart of size reduction is integrated circuits becoming more fragile electrically. In the automotive world, the new trend of fully autonomous driving is seeing tremendous progress recently. Autonomous vehicles must take decisions and perform critical actions such as braking or steering the wheel. Those decisions are taken by electronic modules, that have now very high responsibilities with regards of our safety. It is important to ensure that those modules will operate no matter the kind of disturbances they can be exposed to. The automotive world is a quite harsh environment for electronic systems. A major source of electrical stress is called the Electrostatic Discharge (ESD). It is a very sudden flow of electricity of large amplitude capable of destroying electronic components, or disturb them during their normal operation. This research focuses on functional failures where functionality can be temporarily lost after an ESD with various impact on the vehicle. To guarantee before manufacturing that a module and its components will perform their duty correctly, new analysis and prediction methods are required against soft-failures caused by electrostatic discharges. In this research, different approaches have been explored and proposed towards that goal. First, a modelling method for reproducing the ESD waveforms from the test generator up to the integrated circuit input is presented. It is based on a hierarchical approach where each element of the system is modelled individually, then added to the complete setup model. A practical case of functional failure at silicon-level is analyzed using simulation tools. To acquire more data on this fault, a testchip has been designed. It contains on-chip monitoring structures to measure voltage and current, and monitor function behavior directly at silicon-level. The last part of this research details different analysis methods developed for identifying efficiently functional weaknesses. The methods rely heavily on simulation tools, and prototypes have been implemented to prove the initial concepts. The first method models each function inside the chip individually, using behavioral models, then enables to connect the models together to deduce the full function's robustness. It enables hierarchical analysis of complex integrated circuit designs, to identify potential weak spots inside the circuit that could require more shielding or protection. The second method is focused on constructing equivalent electrical black box models of integrated circuit functions. The goal is to model the IC with a behavioral, black-box model capable of reproducing waveforms in powered conditions during the ESD. In summary, this research work has led to the development of several hardware and software prototypes. It has also highlighted important modelling challenges to solve in future works to achieve better functional robustness against electrostatic discharges

Design, Characterization And Compact Modeling Of Novel Silicon Controlled Rectifier (scr)-based Devices For Electrostatic Discha

Electrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have been standardized as human body model (HBM), machine model (MM), charged device model (CDM) and international electrotechnical commission model (IEC) for control, monitor and test. In additional to the environmental control of ESD events during manufacturing, shipping and assembly, incorporating on-chip ESD protection circuits inside ICs is another effective solution to reduce the ESD-induced damage. This dissertation presents design, characterization, integration and compact modeling of novel silicon controlled rectifier (SCR)-based devices for on-chip ESD protection. The SCR-based device with a snapback characteristic has long been used to form a VSS-based protection scheme for on-chip ESD protection over a broad rang of technologies because of its low on-resistance, high failure current and the best area efficiency. The ESD design window of the snapback device is defined by the maximum power supply voltage as the low edge and the minimum internal circuitry breakdown voltage as the high edge. The downscaling of semiconductor technology keeps on squeezing the design window of on-chip ESD protection. For the submicron process and below, the turn-on voltage and sustain voltage of ESD protection cell should be lower than 10 V and higher than 5 V, respectively, to avoid core circuit damages and latch-up issue. This presents a big challenge to device/circuit engineers. Meanwhile, the high voltage technologies push the design window to another tough range whose sustain voltage, 45 V for instance, is hard for most snapback ESD devices to reach. Based on the in-depth elaborating on the principle of SCR-based devices, this dissertation first presents a novel unassisted, low trigger- and high holding-voltage SCR (uSCR) which can fit into the aforesaid ESD design window without involving any extra assistant circuitry to realize an area-efficient on-chip ESD protection for low voltage applications. The on-chip integration case is studied to verify the protection effectiveness of the design. Subsequently, this dissertation illustrate the development of a new high holding current SCR (HHC-SCR) device for high voltage ESD protection with increasing the sustain current, not the sustain voltage, of the SCR device to the latchup-immune level to avoid sacrificing the ESD protection robustness of the device. The ESD protection cells have been designed either by using technology computer aided design (TCAD) tools or through trial-and-error iterations, which is cost- or time-consuming or both. Also, the interaction of ESD protection cells and core circuits need to be identified and minimized at pre-silicon stage. It is highly desired to design and evaluate the ESD protection cell using simulation program with integrated circuit emphasis (SPICE)-like circuit simulation by employing compact models in circuit simulators. And the compact model also need to predict the response of ESD protection cells to very fast transient ESD events such as CDM event since it is a major ESD failure mode. The compact model for SCR-based device is not widely available. This dissertation develops a macromodeling approach to build a comprehensive SCR compact model for CDM ESD simulation of complete I/O circuit. This modeling approach offers simplicity, wide availability and compatibility with most commercial simulators by taking advantage of using the advanced BJT model, Vertical Bipolar Inter-Company (VBIC) model. SPICE Gummel-Poon (SGP) model has served the ICs industry well for over 20 years while it is not sufficiently accurate when using SGP model to build a compact model for ESD protection SCR. This dissertation seeks to compare the difference of SCR compact model built by using VBIC and conventional SGP in order to point out the important features of VBIC model for building an accurate and easy-CAD implement SCR model and explain why from device physics and model theory perspectives

On-Chip ESD Protection Design: Optimized Clamps

The extensive use of Integrated Circuits (ICs) means complex working conditions for these tiny chips. To guarantee the ICs could work properly in various environments, some special protection strategies are required to improve the reliability of system. From all the possible reliability issues, the electrostatics discharge (ESD) might be the most common one. The peak current of electrostatics can be as high as tens of amperes and the peak voltage can be over thousand voltages. In contrast, the size of semiconductor device fabricated is continuing to scale down, making it even more vulnerable to high level overstress and current surge induced by ESD event. To protect the on-chip semiconductor from damage, some extra clamp cells are put together to consist a network. The network can redirect the superfluous current through the ESD network and clamp the voltage to a low level. In this dissertation, one design concept is introduced that uses the combination of some basic ESD devices to meet different requirements first, and then tries to establish parasitic current path among these devices to further increase the current handling capability. Some design cases are addressed to demonstrate this design concept is valid and efficient: 1. A combination of silicon-controlled-rectifier (SCR) and diode cluster is implemented to resolve the overshoot issue under fast ESD event. 2. A new SCR structure is introduced, which can be used as padding device to increase the clamping voltage without affecting other parameters. Based on this padding device, two design cases are introduced. 3. A controllable SCR clamp structure is presented, which has high current handling capability and can be controlled with by small signal. All these structures and topologies described in this dissertation are compatible with most of popular semiconductor fabrication process