Photo-effects on Current Transport in Back-gate Graphene Field-effect Transistor

Graphene, which has attracted wide attention because of its two-dimensional structure and high carrier mobility, is a promising candidate for potential application in optics and electronics. In this dissertation, the photonic effects on current transport in back-gate graphene field-effect transistor is investigated. Chemical vapor deposition (CVD) on metal provides a promising way for large area, controllability and high quality graphene film. The transfer and back-gate transistor fabrication processes are proposed in this dissertation. The theoretical analysis of photodetector based on back-gate graphene field-effect transistor has been done. It is shown that the photo-electronic current consists of current contributions from photovoltaic, photo-thermoelectric and photo-bolometric effects. A maximum external responsivity close to 0.0009A/W is achieved at 30μW laser power source and 633nm wavelength. The photodiode based on graphene/silicon Schottky barrier is also. A computed 238.8 W-1 photocurrent to dark current ratio normalized by the power source (633nm wavelength and 10mW laser) is obtained. An equivalent circuit model of the graphene/silicon Schottky barrier diode compatible with SPICE simulation is developed and simulated photo-response characteristics are presented using analog behavior modeling which are in close agreement with the theoretical analysis. Besides the optical applications, graphene based-transistors can also be used in applications related to space electronics. The irradiation effects including oxide trap charge and graphene layer traps charges are investigated. A semi-empirical model of graphene back-gate transistors before and after irradiation is predicted

Particle-Based Modeling of Reliability for Millimeter-Wave GaN Devices for Power Amplifier Applications

abstract: In this work, an advanced simulation study of reliability in millimeter-wave (mm-wave) GaN Devices for power amplifier (PA) applications is performed by means of a particle-based full band Cellular Monte Carlo device simulator (CMC). The goal of the study is to obtain a systematic characterization of the performance of GaN devices operating in DC, small signal AC and large-signal radio-frequency (RF) conditions emphasizing on the microscopic properties that correlate to degradation of device performance such as generation of hot carriers, presence of material defects and self-heating effects. First, a review of concepts concerning GaN technology, devices, reliability mechanisms and PA design is presented in chapter 2. Then, in chapter 3 a study of non-idealities of AlGaN/GaN heterojunction diodes is performed, demonstrating that mole fraction variations and the presence of unintentional Schottky contacts are the main limiting factor for high current drive of the devices under study. Chapter 4 consists in a study of hot electron generation in GaN HEMTs, in terms of the accurate simulation of the electron energy distribution function (EDF) obtained under DC and RF operation, taking into account frequency and temperature variations. The calculated EDFs suggest that Class AB PAs operating at low frequency (10 GHz) are more robust to hot carrier effects than when operating under DC or high frequency RF (up to 40 GHz). Also, operation under Class A yields higher EDFs than Class AB indicating lower reliability. This study is followed in chapter 5 by the proposal of a novel π-Shaped gate contact for GaN HEMTs which effectively reduces the hot electron generation while preserving device performance. Finally, in chapter 6 the electro-thermal characterization of GaN-on-Si HEMTs is performed by means of an expanded CMC framework, where charge and heat transport are self-consistently coupled. After the electro-thermal model is validated to experimental data, the assessment of self-heating under lateral scaling is considered.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Design, scaling and reliability of devices for high-performance mixed-signal applications

This research investigates and gains new understanding on how silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device design couples with both performance scaling and reliability for mixed-signal applications (high-frequency and analog). In addition, this work provides methods of using this knowledge to enhance the predictive modeling of performance and reliability for these devices. The primary objective of this effort is to develop a predictive device modeling methodology and simulation framework that can be used to design new mixed-signal device technologies, and can then be used to assess the device performance and reliability concurrently. Ultimately, the goal is to highlight the need for device performance and reliability in a circuit environment, and establish best practices for practical modeling of these constraints and any resulting trade-offs. To support this objective, several specific areas were targeted to fill the existing gaps in knowledge. This includes developing a technology computer-aided-design (TCAD) based integrated simulation framework and methodology to study performance scaling and reliability in complementary SiGe HBTs; identifying factors determining the predictive nature of the simulated device figures-of-merit (FoM); studying electrothermal constraints for scaling SiGe HBTs on thick-film silicon-on-insulator (SOI) to understand its impact on the DC and RF safe-operating-area (SOA) for the device; and performing reliability studies of hot-carrier damage and annealing in npn and pnp SiGe HBT devices in an effort to gain insight into the physical mechanisms involved and to develop fundamental understanding to aid TCAD modeling of hot-carrier damage in these devices. All of these individual studies resulting from the main research tasks are harmoniously tied together by a central theme: to develop a fundamental understanding about how the device design factors influence both performance scaling and reliability. Some of the key existing challenges and knowledge gaps are addressed by analyzing and reconciling the experimental data with simulation results.Ph.D

On variability and reliability of poly-Si thin-film transistors

In contrast to conventional bulk-silicon technology, polysilicon (poly-Si) thin-film transistors (TFTs) can be implanted in flexible substrate and can have low process temperature. These attributes make poly-Si TFT technology more attractive for new applications, such as flexible displays, biosensors, and smart clothing. However, due to the random nature of grain boundaries (GBs) in poly-Si film and self-heating enhanced negative bias temperature instability (NBTI), the variability and reliability of poly-Si TFTs are the main obstacles that impede the application of poly-Si TFTs in high-performance circuits. The primary focus of this dissertation is to develop new design methodologies and modeling techniques for facilitating new applications of poly-Si TFT technology. In order to do that, a physical model is first presented to characterize the GB-induced transistor threshold voltage (V th)variations considering not only the number but also the position and orientation of each GB in 3-D space. The fast computation time of the proposed model makes it suitable for evaluation of GB-induced transistor Vthvariation in the early design phase. Furthermore, a self-consistent electro-thermal model that considers the effects of device geometry, substrate material, and stress conditions on NBTI is proposed. With the proposed modeling methodology, the significant impacts of device geometry, substrate, and supply voltage on NBTI in poly-Si TFTs are shown. From a circuit design perspective, a voltage programming pixel circuit is developed for active-matrix organic light emitting diode (AMOLED) displays for compensating the shift of Vth and mobility in driver TFTs as well as compensating the supply voltage degradation. In addition, a self-repair design methodology is proposed to compensate the GB-induced variations for liquid crystal displays (LCDs) and AMOLED displays. Based on the simulation results, the proposed circuit can decrease the required supply voltage by 20% without performance and yield degradation. In the final section of this dissertation, an optimization methodology for circuit-level reliability tests is explored. To effectively predict circuit lifetime, accelerated aging (i.e. elevated voltage and temperature) is commonly applied in circuit-level reliability tests, such as constant voltage stress (CVS) and ramp voltage stress (RVS) tests. However, due to the accelerated aging, shifting of dominant degradation mechanism might occur leading to the wrong lifetime prediction. To get around this issue, we proposed a technique to determine the proper stress range for accelerated aging tests

NEGATIVE BIAS TEMPERATURE INSTABILITY STUDIES FOR ANALOG SOC CIRCUITS

Negative Bias Temperature Instability (NBTI) is one of the recent reliability issues in sub threshold CMOS circuits. NBTI effect on analog circuits, which require matched device pairs and mismatches, will cause circuit failure. This work is to assess the NBTI effect considering the voltage and the temperature variations. It also provides a working knowledge of NBTI awareness to the circuit design community for reliable design of the SOC analog circuit. There have been numerous studies to date on the NBTI effect to analog circuits. However, other researchers did not study the implication of NBTI stress on analog circuits utilizing bandgap reference circuit. The reliability performance of all matched pair circuits, particularly the bandgap reference, is at the mercy of aging differential. Reliability simulation is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliabilitysusceptible device and NBTI is the most vital failure mechanism for analog circuit in sub-micrometer CMOS technology. This study provides a complete reliability simulation analysis of the on-die Thermal Sensor and the Digital Analog Converter (DAC) circuits and analyzes the effect of NBTI using reliability simulation tool. In order to check out the robustness of the NBTI-induced SOC circuit design, a bum-in experiment was conducted on the DAC circuits. The NBTI degradation observed in the reliability simulation analysis has given a clue that under a severe stress condition, a massive voltage threshold mismatch of beyond the 2mV limit was recorded. Bum-in experimental result on DAC proves the reliability sensitivity of NBTI to the DAC circuitry

Aging-Aware Design Methods for Reliable Analog Integrated Circuits using Operating Point-Dependent Degradation

The focus of this thesis is on the development and implementation of aging-aware design methods, which are suitable to satisfy current needs of analog circuit design. Based on the well known \gm/\ID sizing methodology, an innovative tool-assisted aging-aware design approach is proposed, which is able to estimate shifts in circuit characteristics using mostly hand calculation schemes. The developed concept of an operating point-dependent degradation leads to the definition of an aging-aware sensitivity, which is compared to currently available degradation simulation flows and proves to be efficient in the estimation of circuit degradation. Using the aging-aware sensitivity, several analog circuits are investigated and optimized towards higher reliability. Finally, results are presented for numerous target specifications

Toward a new generation of photonic devices based on the integration of metal oxides in silicon technology

[ES] La búsqueda de nuevas soluciones e ideas innovadoras en el campo de la fotónica de silicio mediante la integración de nuevos materiales con prestaciones únicas es un tema de alta actualidad entre la comunidad científica en fotónica y con un impacto potencial muy alto. Dentro de esta temática, esta tesis pretende contribuir hacia una nueva generación de dispositivos fotónicos basados en la integración de óxidos metálicos en tecnología de silicio. Los óxidos metálicos elegidos pertenecen a la familia de óxidos conductores transparentes (TCO), concretamente el óxido de indio y estaño (ITO) y el óxido de cadmio (CdO), y materiales de cambio de fase (PCM) como el dióxido de vanadio (VO2). Dichos materiales se caracterizan especialmente por una variación drástica de sus propiedades optoelectrónicas, tales como la resistividad o el índice de refracción, frente a un estímulo externo ya sea en forma de temperatura, aplicación de un campo eléctrico o excitación óptica. De esta forma, nuestro objetivo es diseñar, fabricar y demostrar experimentalmente nuevas soluciones y dispositivos clave tales como dispositivos no volátiles, desfasadores y dispositivos con no linealidad óptica. Tales dispositivos podrían encontrar potencial utilidad en diversas aplicaciones que comprenden las comunicaciones ópticas, redes neuronales, LiDAR, computación, cuántica, entre otros. Las prestaciones clave en las que se pretende dar un salto disruptivo son el tamaño y capacidad para una alta densidad de integración, el consumo de potencia, y el ancho de banda.[CA] La recerca de noves solucions i idees innovadores al camp de la fotònica de silici mitjançant la integració de nous materials amb prestacions úniques és un tema d'alta actualitat entre la comunitat científica en fotònica i amb un impacte potencial molt alt. D'aquesta temàtica, aquesta tesi pretén contribuir cap a una nova generació de dispositius fotònics basats en la integració d'òxids metàl·lics en tecnologia de silici. Els òxids metàl·lics elegits pertanyen a la família d'òxids conductors transparents (TCO), concretament l'òxid d'indi i estany (ITO) i l'òxid de cadmi (CdO), i materials de canvi de fase (PCM) com el diòxid de vanadi (VO2). Aquests materials es caracteritzen especialment per una variació dràstica de les propietats optoelectròniques, com ara la resistivitat o l'índex de refracció, davant d'un estímul extern ja siga en forma de temperatura, aplicació d'un camp elèctric o excitació òptica. D'aquesta manera, el nostre objectiu és dissenyar, fabricar i demostrar experimentalment noves solucions i dispositius clau com ara dispositius no volàtils, desfasadors i dispositius amb no-linealitat òptica. Aquests dispositius podrien trobar potencial utilitat en diverses aplicacions que comprenen les comunicacions òptiques, xarxes neuronals, LiDAR, computació, quàntica, entre d'altres. Les prestacions clau en què es pretén fer un salt disruptiu són la grandària i la capacitat per a una alta densitat d'integració, el consum de potència i l'amplada de banda.[EN] The search for new solutions and innovative ideas in the field of silicon photonics through the integration of new materials featuring unique optoelectronic properties is a hot topic among the photonics scientific community with a very high potential impact. Within this topic, this thesis aims to contribute to a new generation of photonic devices based on the integration of metal oxides in silicon technology. The chosen metal oxides belong to the family of transparent conducting oxides (TCOs), namely indium tin oxide (ITO) and cadmium oxide (CdO), and phase change materials (PCMs) such as vanadium dioxide (VO2). These materials are characterized by a drastic variation of their optoelectronic properties, such as resistivity or refractive index, in response to an external stimulus either in the form of temperature, application of an electric field, or optical excitation. Therefore, our objective is to design, fabricate and experimentally demonstrate new solutions and key devices such as non-volatile devices, phase shifters, and devices with optical nonlinearity. Such devices could find potential utility in several applications, including optical communications, neural networks, LiDAR, computing, and quantum. The key features in which we aim to take a leapfrog are footprint and capacity for high integration density, power consumption, and bandwidth.This work is supported in part by grants ACIF/2018/172 funded by Generaliltat Valenciana, and FPU17/04224 funded by MCIN/AEI/10.13039/501100011033 and by “ESF Investing in your future”.Parra Gómez, J. (2022). Toward a new generation of photonic devices based on the integration of metal oxides in silicon technology [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/19088

Self-Heating Effects on the Thermal Noise of Deep Sub-Micron FD-SOI MOSFETs

Self-heating effects became more prominent with the introduction of the modern devices like FD-SOI and low thermal conductivity materials such as SiO2. Consequently, the temperature rise of a device due to its self-heating is pronounced more as the gate lengths shrink and the power density values increase. In analog design, one of the main drawbacks of elevated temperature is the deterioration of the thermal noise performance. For observing the thermal noise performance of FD-SOI MOSFETs, a thermal model for the device self-heating is used. The influence of self-heating on the thermal noise is examined by activating and inactivating the self-heating thermal model and comparing the results. It is shown that self-heating can deteriorate the thermal noise current (up to 18%) and the input referred thermal noise voltage (up to 37%) significantly for short channel FD-SOI devices

A comprehensive study of the short-circuit ruggedness of silicon carbide power MOSFETs

The behavior of Silicon Carbide Power MOSFETs under stressful short circuit conditions is investigated in this paper. Illustration of two different short-circuit failure phenomena for Silicon Carbide Power MOSFETs are thoroughly reported. Experimental evidences and TCAD electro-thermal simulations are exploited to describe and discriminate the failure sources. Physical causes are finally investigated and explained by means of properly calibrated numerical investigations, and are reported along with their effects on devices short-circuit capability