Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

Synthesis and analysis of nonlinear, analog, ultra low power, Bernoulli cell based CytoMimetic circuits for biocomputation

A novel class of analog BioElectronics is introduced for the systematic implementation of ultra-low power microelectronic circuits, able to compute nonlinear biological dynamics. This class of circuits is termed ``CytoMimetic Circuits'', in an attempt to highlight their actual function, which is mimicking biological responses, as observed experimentally. Inspired by the ingenious Bernoulli Cell Formalism (BCF), which was originally formulated for the modular synthesis and analysis of linear, time-invariant, high-dynamic range, logarithmic filters, a new, modified mathematical framework has been conceived, termed Nonlinear Bernoulli Cell Formalism (NBCF), which forms the core mathematical framework, characterising the operation of CytoMimetic circuits. The proposed nonlinear, transistor-level mathematical formulation exploits the striking similarities existing between the NBCF and coupled ordinary differential equations, typically appearing in models of naturally encountered biochemical systems. The resulting continuous-time, continuous-value, low-power CytoMimetic electronic circuits succeed in simulating with good accuracy cellular and molecular dynamics and found to be in very good agreement with their biological counterparts. They usually occupy an area of a fraction of a square millimetre, while consuming between hundreds of nanowatts and few tenths of microwatts of power. The systematic nature of the NBCF led to the transformation of a wide variety of biochemical reactions into nonlinear Log-domain circuits, which span a large area of different biological model types. Moreover, a detailed analysis of the robustness and performance of the proposed circuit class is also included in this thesis. The robustness examination has been conducted via post-layout simulations of an indicative CytoMimetic circuit and also by providing fabrication-related variability simulations, obtained by means of analog Monte Carlo statistical analysis for each one of the proposed circuit topologies. Furthermore, a detailed mathematical analysis that is carefully addressing the effect of process-parameters and MOSFET geometric properties upon subthreshold translinear circuits has been conducted for the fundamental translinear blocks, CytoMimetic topologies are comprised of. Finally, an interesting sub-category of Neuromorphic circuits, the ``Log-Domain Silicon Synapses'' is presented and representative circuits are thoroughly analysed by a novel, generalised BC operator framework. This leads to the conclusion that the BC operator consists the heart of such Log-domain circuits, therefore, allows the establishment of a general class of BC-based silicon synaptic circuits, which includes most of the synaptic circuits, implemented so far in Log-domain.Open Acces

CMOS Impedance Measurement Array for Cell Sensing

Impedance measurement plays a vital role in determining the physical and chemical properties of live cells under different environmental conditions and aids in the development of cellular models for life science research and new medicines to fight disease. In order to improve the fidelity and spatial resolution of bio-impedance measurement systems, cell sensing platforms are being constructed using silicon chips where live cells interact with integrated microelectronic sensors through an on-chip electrode array. Our proposed complementary metal-oxide-semiconductor (CMOS) sensor array measures the impedance of complex cellular samples using a mixed-signal-based frequency response analysis (FRA) approach to extract and convert the real and imaginary parts of the cell impedance. The system is implemented using a synchronous voltage-to-frequency converter designed to operate over an input frequency range from 0.7 Hz to 2 kHz with a programmable nominal resolution up to 16 bits. Unlike previous work, we apply a switched-capacitor-based offset correction scheme to reduce the effect of multiplying integrator input offset on the sensor interface. The chip features an 8×6 surface electrode array of individually-addressable working electrodes connected to four independent impedance extraction channels for parallel data readout. The device is fabricated in a standard 0.18 µm CMOS technology, where each sensor channel consumes only 94 µW from a 1.8 V supply, and has been experimentally verified to provide linear conversion over an input current amplitude range from 40 pA to 60 nA.1 yea