Characterization and Modeling of High Power Microwave Effects in CMOS Microelectronics

The intentional use of high power microwave (HPM) signals to disrupt microelectronic systems is a substantial threat to vital infrastructure. Conventional methods to assess HPM threats involve empirical testing of electronic equipment, which provides no insight into fundamental mechanisms of HPM induced upset. The work presented in this dissertation is part of a broad effort to develop more effective means for HPM threat assessment. Comprehensive experimental evaluation of CMOS digital electronics was performed to provide critical information of the elementary mechanisms that govern the dynamics of HPM effects. Results show that electrostatic discharge (ESD) protection devices play a significant role in the behavior of circuits irradiated by HPM pulses. The PN junctions of the ESD protection devices distort HPM waveforms producing DC voltages at the input of the core logic elements, which produces output bit errors and abnormal circuit power dissipation. The dynamic capacitance of these devices combines with linear parasitic elements to create resonant structures that produce nonlinear circuit dynamics such as spurious oscillations. The insight into the fundamental mechanisms this research has revealed will contribute substantially to the broader effort aimed at identifying and mitigating susceptibilities in critical systems. Also presented in this work is a modeling technique based on scalable analytical circuit models that accounts for the non-quasi-static behavior of the ESD protection PN junctions. The results of circuit simulations employing these device models are in excellent agreement with experimental measurements, and are capable of predicting the threshold of effect for HPM driven non-linear circuit dynamics. For the first time, a deterministic method of evaluating HPM effects based on physical, scalable device parameters has been demonstrated. The modeling presented in this dissertation can be easily integrated into design cycles and will greatly aid the development of electronic systems with improved HPM immunity

Microwave techniques and applications for semiconductor quantum dot mode-locked lasers

Semiconductor mode-locked lasers (MLLs) are important as compact and cost-effective sources of picosecond or sub-picosecond optical pulses with moderate peak powers. They have potential use in various fields including optical interconnects for clock distribution at an inter-chip/intra-chip level as well as high bit-rate optical time division multiplexing (OTDM), diverse waveform generation, and microwave signal generation. However, there are still several challenges to conquer for engineering applications. Semiconductor MLLs sources have generally not been able to match the noise performance and pulse quality of the best solid-state mode-locked lasers. For improving the characteristics of semiconductor mode-locked lasers, research on both the material/device design and stabilization mechanism is necessary. In this dissertation, by extending the net-gain modulation phasor approach based on a microwave photonics perspective, a convenient, yet powerful analytical model is derived and experimentally verified for the cavity design of semiconductor two-section passive MLLs. This model will also be useful in designing the next generation quantum dot (QD) MLL capable of stable operation from 20°C to 100°C for optical interconnects applications. The compact optical generation of microwave signals using a monolithic passive QD MLL is investigated. Relevant equations for the efficient conversion of electrical to optical to electrical (EOE) energy are derived and the device principles are described. In order to verify the function of a QD MLL as an RF signal generator, the integration with a rectangular patch antenna system is also studied. Furthermore, combined with the reconfigurable function, the multi-section QD MLL will be a promising candidate of the compact, efficient RF signal source in wireless, beam steering, and satellite communication applications. The noise performance is a key element for semiconductor MLLs in OTDM communications. The external stabilization methods to improve the timing stability in passive MLLs have been studied and an all-microwave measurement technique has also been developed to determine the pulse-to-pulse rms timing jitter. Compared to the conventional optical cross-correlation technique, the new method provides an alternative and simple approach to characterize the timing jitter in a passive MLL. The average pulse-to-pulse rms timing jitter is reduced to 32 fs/cycle under external optical feedback stabilization

Modeling of Silicon Photonic Devices for Optical Interconnect Transceiver Circuit Design

Optical interconnect system efficiency is dependent on the ability to optimize the transceiver circuitry for low-power and high-bandwidth operation, motivating co-simulation environments with compact optical device simulation models. This chapter presents compact Verilog-A silicon carrier-injection and carrier-depletion ring modulator models which accurately capture both nonlinear electrical and optical dynamics. Experimental verification of the carrier-injection ring modulator model is performed both at 8 Gb/s with symmetric drive signals to study the impact of pre-emphasis pulse duration, pulse depth, and dc bias, and at 9 Gb/s with a 65-nm CMOS driver capable of asymmetric pre-emphasis pulse duration. Experimental verification of the carrier-depletion ring modulator model is performed at 25 Gb/s with a 65-nm CMOS driver capable of asymmetric equalization

Wide Band Gap Devices and Their Application in Power Electronics

Power electronic systems have a great impact on modern society. Their applications target a more sustainable future by minimizing the negative impacts of industrialization on the environment, such as global warming effects and greenhouse gas emission. Power devices based on wide band gap (WBG) material have the potential to deliver a paradigm shift in regard to energy efficiency and working with respect to the devices based on mature silicon (Si). Gallium nitride (GaN) and silicon carbide (SiC) have been treated as one of the most promising WBG materials that allow the performance limits of matured Si switching devices to be significantly exceeded. WBG-based power devices enable fast switching with lower power losses at higher switching frequency and hence, allow the development of high power density and high efficiency power converters. This paper reviews popular SiC and GaN power devices, discusses the associated merits and challenges, and finally their applications in power electronics

Architecture, Voltage and Components for a Turboelectric Distributed Propulsion Electric Grid

The development of a wholly superconducting turboelectric distributed propulsion system presents hide unique opportunities for the aerospace industry. However, this transition from normally conducting systems to superconducting systems significantly increases the equipment complexity necessary to manage the electrical power systems. Due to the low technology readiness level (TRL) nature of all components and systems, current Turboelectric Distributed Propulsion (TeDP) technology developments are driven by an ambiguous set of system-level electrical integration standards for an airborne microgrid system (Figure 1). While multiple decades' worth of advancements are still required for concept realization, current system-level studies are necessary to focus the technology development, target specific technological shortcomings, and enable accurate prediction of concept feasibility and viability. An understanding of the performance sensitivity to operating voltages and an early definition of advantageous voltage regulation standards for unconventional airborne microgrids will allow for more accurate targeting of technology development. Propulsive power-rated microgrid systems necessitate the introduction of new aircraft distribution system voltage standards. All protection, distribution, control, power conversion, generation, and cryocooling equipment are affected by voltage regulation standards. Information on the desired operating voltage and voltage regulation is required to determine nominal and maximum currents for sizing distribution and fault isolation equipment, developing machine topologies and machine controls, and the physical attributes of all component shielding and insulation. Voltage impacts many components and system performance

Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs

Silicon Carbide MOSFETs are shown in research to outperform Silicon counterparts on many performance metrics, including switching rates and power losses. To further improve their performance, trench and double-trench structures have recently been developed. To replace conventional planar SiC MOSFETs, besides the performance parameters which are mostly stated in datasheets, reliability studies under stress are also needed. This thesis presents a comprehensive comparison between 3rd generation trench SiC power MOSFETs, namely symmetrical double-trench and asymmetrical trench with planar SiC power MOSFETs on four aspects of: switching slew rates (dI/dt & dV/dt), crosstalk characteristics, bias temperature instability and power cycling stability.First, the dynamic performance in both 1st quadrant and 3rd quadrant has been eval- uated on the differences in stress by dI/dt & dV/dt and resultant losses. This is key in understanding many other reliability criterions, i.e. severity of crosstalk induced switchings. In the 1st quadrant, the source current and drain-source voltage switching rates at both turn-ON and turn-OFF are measured under a range of test conditions. Both the symmetrical and asymmetrical trench MOSFETs have up to 2 times faster voltage and current slew rates compared with the planar one. They also indicate only slight changes in switching rate with junction temperature. In the 3rd quadrant, the reverse recovery peak current and total reverse recovery charge are measured with respect to junction temper- ature and load current level. Both the symmetrical and asymmetrical trench MOSFETs have less than half of the reverse recovery charge of that of the planar SiC MOSFET.In the evaluation of crosstalk characteristics, peak shoot-through current and induced gate voltage at crosstalk are measured with respect to junction temperature and external gate resistance. With particularly large external gate resistances connected to intentionally induce parasitic turn-ON, the symmetrical double-trench MOSFET is shown to be more prone to crosstalk with 23 A peak shoot-through current measured while it is only 10 A for asymmetrical trench and 4 A for planar MOSFET under similar test conditions. As the temperature increase, the peak shoot-through current drops for the symmetrical double-trench, while constant for the asymmetrical trench and rising for the planar device.Threshold voltage drift is also measured to reflect the degradation happened with bias temperature instability at various junction temperatures, stressing voltages and time periods. Under low-magnitude gate stress (within the range of datasheets) in both positive and negative bias cases, there is more threshold drift observed on the two trench MOSFETs at all junction temperatures than the planar MOSFET. When the stress magnitude is raised, there is less threshold drift observed on the two trench MOSFETs.To evaluate the ruggedness in continuous switchings, the devices are placed under repetitive turn-ON events. The thermal performance under such operation are compared. The asymmetrical trench MOSFET experiences the highest case temperature rise while the least is observed for the planar MOSFET. With an external heatsink equipped to achieve more efficient cooling, the repetitive turn-ON test transforms into the conventional power cycling. In this condition, both the symmetrical and asymmetrical trench MOSFETs fail earlier than the degraded (but not failed) planar MOSFET

Electronic operation and control of high-intensity gas-discharge lamps

The ever increasing amount of global energy consumption based on the application of fossil fuels is threatening the earth’s natural resources and environment. Worldwide, grid-based electric lighting consumes 19 % of total global electricity production. For this reason the transition towards energy efficient lighting plays an important environmental role. One of the key technologies in this transition is High-Intensity Discharge (HID) lighting. The technical revolution in gas-discharge lamps has resulted in the highlyefficient lamps that are available nowadays. As with most energy efficient light solutions, all HID lighting systems require a ballast to operate. Traditionally, magnetic ballast designs were the only choice available for HID lighting systems. Today, electronic lampdrivers can offer additional power saving, flicker free operation, and miniaturisation. Electronic lamp operation enables additional degrees of freedom in lamp-current control over the conventional electro-magnetic (EM) ballasts. The lamp-driver system performance depends on both the dynamics of the lamp and the driver. This thesis focuses on the optimisation of electronically operated HID systems, in terms of highly-efficient lamp-driver topologies and, more specifically, lamp-driver interaction control. First, highly-efficient power topologies to operate compact HID lamps on low-frequency-square-wave (LFSW) current are explored. The proposed two-stage electronic lamp-driver consists of a Power Factor Corrector (PFC) stage that meets the power utility standards. This converter is coupled to a stacked buck converter that controls the lamp-current. Both stages are operated in Zero Voltage Switching (ZVS) mode in order to reduce the switching losses. The resulting two-stage lamp-drivers feature flexible controllability, high efficiency, and high power density, and are suitable for power sandwich packaging. Secondly, lamp-driver interaction (LDI) has been studied in the simulation domain and control algorithms have been explored that improve the stability, and enable system optimisation. Two HID lamp models were developed. The first model describes the HID lamp’s small-signal electrical behaviour and its purpose is to aid to study the interaction stability. The second HID lamp model has been developed based on physics equations for the arc column and the electrode behaviour, and is intended for lampdriver simulations and control applications. Verification measurements have shown that the lamp terminal characteristics are present over a wide power and frequency range. Three LDI control algorithms were explored, using the proposed lampmodels. The first control principle optimises the LDI for a broad range of HID lamps operated at normal or reduced power. This approach consists of two control loops integrated into a fuzzy-logic controller that stabilises the lamp-current and optimises the commutation process. The second control problem concerns the application of ultra high performance (UHP) HID lamps in projection applications that typically set stringent requirements on the quality of the light generated by these lamps, and therefore the lampcurrent. These systems are subject to periodic disturbances synchronous with the LFSW commutation period. Iterative learning control (ILC) has been examined. It was experimentally verified that this algorithm compensates for repetitive disturbances. Third, Electronic HID operation also opens the door for continuous HID lamp dimming that can provide additional savings. To enable stable dimming, an observer-based HID lamp controller has been developed. This controller sets a stable minimum dim-level and monitors the gas-discharge throughout lamp life. The HID lamp observer derives physical lamp state signals from the HID arc discharge physics and the related photometric properties. Finally, practical measurements proved the proposed HID lamp observer-based control principle works satisfactorily

Generadores de pulso del orden de nanosegundos para control de calidad y diagnosis de las cámaras de telescopios Cherenkov

Tesis inédita de la Universidad Complutense de Madrid, Facultad de Ciencias Físicas, Departamento de Física Aplicada III (Electricidad y Electrónica), leída el 30-11-2015Depto. de Estructura de la Materia, Física Térmica y ElectrónicaFac. de Ciencias FísicasTRUEunpu

Chaotic Oscillations in CMOS Integrated Circuits

Chaos is a purely mathematical term, describing a signal that is aperiodic and sensitive to initial conditions, but deterministic. Yet, engineers usually see it as an undesirable effect to be avoided in electronics. The first part of the dissertation deals with chaotic oscillation in complementary metal-oxide-semiconductor integrated circuits (CMOS ICs) as an effect behavior due to high power microwave or directed electromagnetic energy source. When the circuit is exposed to external electromagnetic sources, it has long been conjectured that spurious oscillation is generated in the circuits. In the first part of this work, we experimentally and numerically demonstrate that these spurious oscillations, or out-of-band oscillations are in fact chaotic oscillations. In the second part of the thesis, we exploit a CMOS chaotic oscillator in building a cryptographic source, a random number generator. We first demonstrate the presence of chaotic oscillation in standard CMOS circuits. At radio frequencies, ordinary digital circuits can show unexpected nonlinear responses. We evaluate a CMOS inverter coupled with electrostatic discharging (ESD) protection circuits, designed with 0.5 μm CMOS technology, for their chaotic oscillations. As the circuit is driven by a direct radio frequency injection, it exhibits a chaotic dynamics, when the input frequency is higher than the typical maximum operating frequency of the CMOS inverter. We observe an aperiodic signal, a broadband spectrum, and various bifurcations in the experimental results. We analytically discuss the nonlinear physical effects in the given circuit : ESD diode rectification, DC bias shift due to a non-quasi static regime operation of the ESD PN-junction diode, and a nonlinear resonant feedback current path. In order to predict these chaotic dynamics, we use a transistor-based model, and compare the model's performance with the experimental results. In order to verify the presence of chaotic oscillations mathematically, we build on an ordinary differential equation model with the circuit-related nonlinearities. We then calculate the largest Lyapunov exponents to verify the chaotic dynamics. The importance of this work lies in investigating chaotic dynamics of standard CMOS ICs that has long been conjectured. In doing so, we experimentally and numerically give evidences for the presence of chaotic oscillations. We then report on a random number generator design, in which randomness derives from a Boolean chaotic oscillator, designed and fabricated as an integrated circuit. The underlying physics of the chaotic dynamics in the Boolean chaotic oscillator is given by the Boolean delay equation. According to numerical analysis of the Boolean delay equation, a single node network generates chaotic oscillations when two delay inputs are incommensurate numbers and the transition time is fast. To test this hypothesis physically, a discrete Boolean chaotic oscillator is implemented. Using a CMOS 0.5 μm process, we design and fabricate a CMOS Boolean chaotic oscillator which consists of a core chaotic oscillator and a source follower buffer. Chaotic dynamics are verified using time and frequency domain analysis, and the largest Lyapunov exponents are calculated. The measured bit sequences do make a suitable randomness source, as determined via National Institute of Standards and Technology (NIST) standard statistical tests version 2.1