Determination of key device parameters for short- and long-channel Schottky-type carbon nanotube field-effect transistors

The Schottky barrier, contact resistance and carrier mobility in carbon nanotube (CNT) field-effect transistors (FETs) are discussed in detail in this thesis. Novel extraction methods and definitions are proposed for these parameters. A technology comparison with other emerging transistor technologies and a performance projection study are also presented. A Schottky barrier height extraction method for CNTFETs considering one-dimensional (1D) conditions is developed. The methodology is applied to simulation and experimental data of CNTFETs feasible for manufacturing. Y-function-based methods (YFMs) have been applied to simulation and experimental data in order to extract a contact resistance for CNTFETs. Both extraction methods are more efficient and accurate than other conventional approaches. Practical mobility expressions are derived for CNTFETs covering the ballistic as well as the non-ballistic transport regime which enable a straightforward evaluation of the transport in CNTs. They have been applied to simulation and experimental data of devices with different channel lengths and Schottky barrier heights. A comparison of fabricated emerging transistors based on similar criteria for various application scenarios reveals CNTFETs as promising candidates to compete with Si-based technologies in low-power static and dynamic applications. A performance projection study is suggested for specific applications in terms of the studied design parameters

Device and circuit-level models for carbon nanotube and graphene nanoribbon transistors

Metal-oxide semiconductor field-effect transistor (MOSFET) scaling throughout the years has enabled us to pack million of MOS transistors on a single chip to keep in pace with Moore’s Law. After forty years of advances in integrated circuit (IC) technology, the scaling of silicon (Si) MOSFET has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. The latest technological advancement has led to a low power, high-density and high-speed generation of processor. Nevertheless, the scaling of the Si MOSFET below 22 nm may soon meet its’ fundamental physical limitations. This threshold makes the possible use of novel devices and structures such as carbon nanotube field-effect transistors (CNTFETs) and graphene nanoribbon field-effect transistors (GNRFETs) for future nanoelectronics. The investigation explores the potential of these amazing carbon structures that exceed MOSFET capabilities in term of speed, scalability and power consumption. The research findings demonstrate the potential integration of carbon based technology into existing ICs. In particular, a simulation program with integrated circuit emphasis (SPICE) model for CNTFET and GNRFET in digital logic applications is presented. The device performance of these circuit models and their design layout are then compared to 45 nm and 90 nm MOSFET for benchmarking. It is revealed through the investigation that CNT and GNR channels can overcome the limitations imposed by Si channel length scaling and associated short channel effects while consuming smaller channel area at higher current density

Semi-analytical model for carbon nanotube and graphene nanoribbon transistors

Carbon nanotubes and graphene provide high carrier mobility for ballistic transport, high carrier velocity for fast switching, and excellent mechanical and thermal conductivity. As a result, they are widely considered as next generation candidate materials for nanoelectronics. In this thesis, I first propose a physics-based semi-analytical model for Schottky-barrier (SB) carbon nanotube (CNT) and graphene nanoribbon (GNR) transistors. The model reduces the computational complexity in the two critical but time-consuming steps, namely the calculation of the tunneling probability and the self-consistent evaluation of the surface potential in the transistor channel. Since SB-type CNT and GNR transistors exhibit ambipolar conduction that is not preferable in digital applications, I further propose a semi-analytical model for the double-gate transistor structure that is able to control the ambipolar conduction in-field. Future directions, including the modeling of new CNT and GNR devices and novel circuits based on the in-field controllability of ambipolar conduction, will also be described

High-Performance and Energy-Efficient Leaky Integrate-and-Fire Neuron and Spike Timing-Dependent Plasticity Circuits in 7nm FinFET Technology

In designing neuromorphic circuits and systems, developing compact and energy-efficient neuron and synapse circuits is essential for high-performance on-chip neural architectures. Toward that end, this work utilizes the advanced low-power and compact 7nm FinFET technology to design leaky integrate-and-fire (LIF) neuron and spike-timing-dependent plasticity (STDP) circuits. In the proposed STDP circuit, only six FinFETs and three small capacitors (two 10fF and 20fF) have been utilized to realize STDP learning. Moreover, 12 transistors and two capacitors (20fF) have been employed for designing the LIF neuron circuit. The evaluation results demonstrate that besides 60% area saving, the proposed STDP circuit achieves 68% improvement in total average power consumption and 43% lower energy dissipation compared to previous works. The proposed LIF neuron circuit demonstrates 34% area saving, 46% power, and 40% energy saving compared to its counterparts. The neuron can also tune the firing frequency within 5MHz-330MHz using an external control voltage. These results emphasize the potential of the proposed neuron and STDP learning circuits for compact and energy-efficient neuromorphic computing systems

Analysis and design of current mode logic based on CNTFET

In this letter we present a current mode gate based on differential pair as an application of carbon nanotube field effect transistors (CNTFETs). The proposed circuit has two output logic gates: one is NAND, and the other is AND. To simplify the circuit realization we use all CNTFETs of the same type, all with the same lengths and carbon nanotube symmetry indices (n, m). Complex circuits could be obtained in current mode replicating the differential pair CNTFET along the current path. The proposed procedure allows simulation of transfer characteristics from voltage input to current output but also from voltage input to voltage output. Moreover, we can measure simulated power dissipation and delay times

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Overview of carbon-based circuits and systems

This paper presents an overview of the state of the art on carbon-based circuits and systems made up of carbon nanotubes and graphene transistors. A tutorial description of the most important devices and their potential benefits and limitations is given, trying to identify their suitability to implement analog and digital circuits and systems. Main electrical models reported so far for the design of carbon-based field-effect devices are surveyed, and the main sizing parameters required to implement such devices in practical integrated circuits are analyzed. The solutions proposed by cutting-edge integrated circuits and devices are discussed, identifying current trends, challenges and opportunities for the circuits and systems community1