Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed

Design and multiplier-less realization of matched filters with variable fractional delay for software radio receivers

The 47th Midwest Symposium on Circuits and Systems Conference, Salt Lake City, Utah, USA, 25-28 July 2004This paper studies the design and multiplier-less realization of variable fractional delay matched filters (VFD-MFs), which provide matching filtering and variable fractional delay of the filter output. It offers greater flexibility and lower delay in symbol-timing adjustment than directly cascading a match filter with a fractional delayer. The design of VFD-MFs, which can be viewed as a variable digital filter (VDF) design problem subject to the matched filtering condition, is formulated as a second order cone programming (SOCP) problem with least square design criteria. The proposed VFD-MFs can be efficiently implemented using the Farrow structure. By employing sum-of-power-of-two (SOPOT) coefficients and the multiplier block (MB) technique, very efficient multiplier-less realization of the VFD-MF with low hardware complexity is obtained. A design example is given to demonstrate the effectiveness of the proposed approach.published_or_final_versio

Digital resampling and timing recovery in QAM systems

Digital resampling is a process that converts a digital signal from one sampling rate to another. This process is performed by means of interpolating between the input samples to produce output samples at an output sampling rate. The digital interpolation process is accomplished with an interpolation filter. The problem of resampling digital signals at an output sampling rate that is incommensurate with the input sampling rate is the first topic of this thesis. This problem is often encountered in practice, for example in multiplexing video signals from different sources for the purpose of distribution. There are basically two approaches to resample the signals. Both approaches are thoroughly described and practical circuits for hardware implementation are provided. A comparison of the two circuits shows that one circuit requires a division to compute the new sampling times. This time scaling operation adds complexity to the implementation with no performance advantage over the other circuit, and makes the 'division free' circuit the preferred one for resampling. The second topic of this thesis is performance analysis of interpolation filters for Quadrature Amplitude Modulation (QAM) signals in the context of timing recovery. The performance criterion of interest is Modulation Error Ratio (MER), which is considered to be a very useful indicator of the quality of modulated signals in QAM systems. The methodology of digital resampling in hardware is employed to describe timing recovery circuits and propose an approach to evaluate the performance of interpolation filters. A MER performance analysis circuit is then devised. The circuit is simulated with MATLAB/Simulink as well as implemented in Field Programmable Gate Array (FPGA). Excellent agreement between results obtained from simulation and hardware implementation proves the validity of the methodology and practical application of the research works

Contribution to Efficient Use of Narrowband Radio Channel

Předkládaná práce se soustředí na problematiku využívání úzkopásmového rádiového kanálu rádiovými modemy, které jsou určené pro průmyslové aplikace pozemní pohyblivé rádiové služby, specifikované v dominantní míře Evropským standardem ETSI EN 300 113. Tato rádiová zařízení se používají v kmitočtových pásmech od 30 MHz do 1 GHz s nejčastěji přidělovanou šířkou pásma 25 kHz a ve většině svých instalací jsou využívána ve fixních nebo mobilních bezdrátových sítích. Mezi typické oblasti použití patří zejména datová telemetrie, aplikace typu SCADA, nebo monitorování transportu strategických surovin. Za hlavní znaky popisovaného systému lze označit komunikační pokrytí značných vzdáleností, dané především vysokou výkonovou účinnosti datového přenosu a využívaní efektivních přístupových technik na rádiový kanál se semiduplexním komunikačním režimem. Striktní požadavky na elektromagnetickou kompatibilitu umožňují těmto zařízením využívat spektrum i v oblastech kmitočtově blízkým jiným komunikačním systémům bez nutnosti vkládání dodatečných ochranných frekvenčních pásem. Úzkopásmové rádiové komunikační systémy, v současnosti používají převážně exponenciální digitální modulace s konstantní modulační obálkou zejména z důvodů velice striktních omezení pro velikost výkonu vyzářeného do sousedního kanálu. Dosahují tak pouze kompromisních hodnot komunikační účinnosti. Úpravy limitů příslušných rádiových parametrů a rychlý rozvoj prostředků číslicového zpracování signálu v nedávné době, dnes umožňují ekonomicky přijatelné využití spektrálně efektivnějších modulačních technik i v těch oblastech, kde je prioritní využívání úzkých rádiových kanálů. Cílem předkládané disertační práce je proto výzkum postupů směřující ke sjednocení výhodných vlastností lineárních a nelineárních modulací v moderní konstrukci úzkopásmového rádiového modemu. Účelem tohoto výzkumu je efektivní a „ekologické“ využívání přidělené části frekvenčního spektra. Mezi hlavní dílčí problémy, jimiž se předkládaná práce zabývá, lze zařadit zejména tyto: Nyquistova modulační filtrace, navrhovaná s ohledem na minimalizaci nežádoucích elektromagnetických interferencí, efektivní číslicové algoritmy frekvenční demodulace a rychlé rámcové a symbolové synchronizace. Součástí práce je dále analýza navrhovaného řešení z pohledu celkové konstrukce programově definovaného rádiového modemu v rovině simulací při vyšetřování robustnosti datového přenosu rádiovým kanálem s bílým Gaussovským šumem nebo kanálem s únikem v důsledku mnohacestného šíření signálu. Závěr práce je pak zaměřen na prezentování výsledků praktické části projektu, v níž byly testovány, měřeny a analyzovány dvě prototypové konstrukce rádiového zařízení. Tato finální část práce obsahuje i praktická doporučení, vedoucí k vyššímu stupni využitelnosti spektrálně efektivnějších komunikačních režimů v oblasti budoucí generace úzkopásmových zařízení pozemní pohyblivé rádiové služby.he industrial narrowband land mobile radio (LMR) devices, as considered in this dissertation project, has been subject to European standard ETSI EN 300 113. The system operates on frequencies between 30 MHz and 1 GHz, with channel separations of up to 25 kHz, and is intended for private, fixed, or mobile, radio packet switching networks. Data telemetry, SCADA, maritime and police radio services; traffic monitoring; gas, water, and electricity producing factories are the typical system applications. Long distance coverage, high power efficiency, and efficient channel access techniques in half duplex operation are the primary advantages the system relays on. Very low level of adjacent channel power emissions and robust radio receiver architectures, with high dynamic range, enable for a system’s coexistence with various communication standards, without the additional guard band frequency intervals. On the other hand, the strict limitations of the referenced standard as well as the state of the technology, has hindered the increase in communication efficiency, with which the system has used its occupied bandwidth. New modifications and improvements are needed to the standard itself and to the up-to-date architectures of narrowband LMR devices, to make the utilization of more efficient modes of system operation practically realizable. The main objective of this dissertation thesis is therefore to find a practical way how to combine the favorable properties of the advanced nonlinear and linear digital modulation techniques in a single digital modem solution, in order to increase the efficiency of the narrowband radio channel usage allocated to the new generation of the industrial LMR devices. The main attention is given to the particular areas of digital modem design such as proposal of the new family of the Nyquist filters minimizing the adjacent channel interference, design and analysis of the efficient algorithms for frequency discrimination, fast frame and symbol

BASEBAND RADIO MODEM DESIGN USING GRAPHICS PROCESSING UNITS

A modern radio or wireless communications transceiver is programmed via software and firmware to change its functionalities at the baseband. However, the actual implementation of the radio circuits relies on dedicated hardware, and the design and implementation of such devices are time consuming and challenging. Due to the need for real-time operation, dedicated hardware is preferred in order to meet stringent requirements on throughput and latency. With increasing need for higher throughput and shorter latency, while supporting increasing bandwidth across a fragmented spectrum, dedicated subsystems are developed in order to service individual frequency bands and specifications. Such a dedicated-hardware-intensive approach leads to high resource costs, including costs due to multiple instantiations of mixers, filters, and samplers. Such increases in hardware requirements in turn increases device size, power consumption, weight, and financial cost. If it can meet the required real-time constraints, a more flexible and reconfigurable design approach, such as a software-based solution, is often more desirable over a dedicated hardware solution. However, significant challenges must be overcome in order to meet constraints on throughput and latency while servicing different frequency bands and bandwidths. Graphics processing unit (GPU) technology provides a promising class of platforms for addressing these challenges. GPUs, which were originally designed for rendering images and video sequences, have been adapted as general purpose high-throughput computation engines for a wide variety of application areas beyond their original target domains. Linear algebra and signal processing acceleration are examples of such application areas. In this thesis, we apply GPUs as software-based, baseband radios and demonstrate novel, software-based implementations of key subsystems in modern wireless transceivers. In our work, we develop novel implementation techniques that allow communication system designers to use GPUs as accelerators for baseband processing functions, including real-time filtering and signal transformations. More specifically, we apply GPUs to accelerate several computationally-intensive, frontend radio subsystems, including filtering, signal mixing, sample rate conversion, and synchronization. These are critical subsystems that must operate in real-time to reliably receive waveforms. The contributions of this thesis can be broadly organized into 3 major areas: (1) channelization, (2) arbitrary resampling, and (3) synchronization. 1. Channelization: a wideband signal is shared between different users and channels, and a channelizer is used to separate the components of the shared signal in the different channels. A channelizer is often used as a pre-processing step in selecting a specific channel-of-interest. A typical channelization process involves signal conversion, resampling, and filtering to reject adjacent channels. We investigate GPU acceleration for a particularly efficient form of channelizer called a polyphase filterbank channelizer, and demonstrate a real-time implementation of our novel channelizer design. 2. Arbitrary resampling: following a channelization process, a signal is often resampled to at least twice the data rate in order to further condition the signal. Since different communication standards require different resampling ratios, it is desirable for a resampling subsystem to support a variety of different ratios. We investigate optimized, GPU-based methods for resampling using polyphase filter structures that are mapped efficiently into GPU hardware. We investigate these GPU implementation techniques in the context of interpolation (integer-factor increases in sampling rate), decimation (integer-factor decreases in sampling rate), and rational resampling. Finally, we demonstrate an efficient implementation of arbitrary resampling using GPUs. This implementation exploits specialized hardware units within the GPU to enable efficient and accurate resampling processes involving arbitrary changes in sample rate. 3. Synchronization: incoming signals in a wireless communications transceiver must be synchronized in order to recover the transmitted data properly from complex channel effects such as thermal noise, fading, and multipath propagation. We investigate timing recovery in GPUs to accelerate the most computationally intensive part of the synchronization process, and correctly align the incoming data symbols in the receiver. Furthermore, we implement fully-parallel timing error detection to accelerate maximum likelihood estimation

An FPGA Implementation of Carrier Phase and Symbol Timing Synchronization for 16-APSK

Proper synchronization between a transmitter and receiver, in terms of carrier phase and symbol timing, is critical for reliable communication. Carrier phase synchronization is related to the frequency translation hardware, where perfect synchronization means that the local oscillators of the transmitter’s upconverter and receiver’s downconverter are aligned in phase and frequency. Timing synchronization is related to the analog-to-digital converter in the receiver, where perfect synchronization means that samples of the received signal are taken at transmitted symbol times. Perfect synchronization is unlikely in practical systems for a number of reasons, including hardware limitations and the independence of the transmitter and receiver. This thesis explores an FPGA implementation of a PLL-based carrier phase and symbol timing synchronization subsystem as part of a 16-APSK aeronautical telemetry receiver. The theory behind this subsystem is presented, and the hardware implementation of each component is described. Results demonstrate successful demodulation of a test signal, and system performance is shown to be comparable to double-precision floating point simulations in terms of error vector magnitude, synchronization lock time, and BER