Combined Security and Schedulability Analysis for MILS Real-Time Critical Architectures

Real-time critical systems have to comply with stringent timing constraints, otherwise, disastrous consequences can occur at runtime. A large effort has been made to propose models and tools to verify timing constraints by schedulability analysis at the early stages of system designs. Fewer efforts have been made on verifying the security properties in these systems despite the fact that sinister consequences can also happen if these properties are compromised. In this article, we investigate how to jointly verify security and timing constraints. We show how to model a security architecture (MILS) and how to verify both timing constraints and security properties. Schedulability is investigated by the mean of scheduling analysis methods implemented into the Cheddar scheduling analyzer. Experiments are conducted to show the impact that improving security has on the schedulability analysis

Partitioned System with XtratuM on PowerPC

XtratuM is a real-time hypervisor originally built on x86 architecture. It is designed referencing the concept of partitioned system. The main work in this thesis is to implement XtratuM in PowerPC architecture.Zhou, R. (2009). Partitioned System with XtratuM on PowerPC. http://hdl.handle.net/10251/12738Archivo delegad

Tighter Integration of Drivers and Protocols in a AADL-based Code Generation Process

Model-based engineering provides an appealing frame- work for the precise modeling and analysis of embed- ded systems. Architecture Description Languages provide a clear and precise semantics to address multiple analy- sis dimensions: scheduling, fault, resource accounting, etc. This is completed by code generation tools that generate all required glue code to enable intercommunication between components and associated configuration mechanisms. The diversity of embedded targets requires extended con- figuration to support multiple devices, operating systems but also compilation toolchains. Yet, those are usually hard- wired in the code generation process. In this paper, we propose several patterns to support model- level configuration of the target, but also increased analysis capabilities in the context of the AADLv2