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Silicon compilation
Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory
Algorithmic techniques for physical design : macro placement and under-the-cell routing
With the increase of chip component density and new manufacturability constraints imposed by modern technology nodes, the role of algorithms for electronic design automation is key to the successful implementation of integrated circuits. Two of the critical steps in the physical design flows are macro placement and ensuring all design rules are honored after timing closure.
This thesis proposes contributions to help in these stages, easing time-consuming manual steps and helping physical design engineers to obtain better layouts in reduced turnaround time.
The first contribution is under-the-cell routing, a proposal to systematically connect standard cell components via lateral pins in the lower metal layers. The aim is to reduce congestion in the upper metal layers caused by extra metal and vias, decreasing the number of design rule violations. To allow cells to connect by abutment, a standard cell library is enriched with instances containing lateral pins in a pre-selected sharing track. Algorithms are proposed to maximize the numbers of connections via lateral connection by mapping placed cell instances to layouts with lateral pins, and proposing local placement modifications to increase the opportunities for such connections. Experimental results show a significant decrease in the number of pins, vias, and in number of design rule violations, with negligible impact on wirelength and timing.
The second contribution, done in collaboration with eSilicon (a leading ASIC design company), is the creation of HiDaP, a macro placement tool for modern industrial designs. The proposed approach follows a multilevel scheme to floorplan hierarchical blocks, composed of macros and standard cells. By exploiting RTL information available in the netlist, the dataflow affinity between these blocks is modeled and minimized to find a macro placement with good wirelength and timing properties. The approach is further extended to allow additional engineer input, such as preferred macro locations, and also spectral and force methods to guide the floorplanning search.
Experimental results show that the layouts generated by HiDaP outperforms those obtained by a state-of-the-art EDA physical design software, with similar wirelength and better timing when compared to manually designed tape-out ready macro placements. Layouts obtained by HiDaP have successfully been brought to near timing closure with one to two rounds of small modifications by physical design engineers. HiDaP has been fully integrated in the design flows of the company and its development remains an ongoing effort.A causa de l'increment de la densitat de components en els xip i les noves restriccions de disseny imposades pels últims nodes de fabricació, el rol de l'algorísmia en l'automatització del disseny electrònic ha esdevingut clau per poder implementar circuits integrats. Dos dels passos crucials en el procés de disseny físic és el placement de macros i assegurar la correcció de les regles de disseny un cop les restriccions de timing del circuit són satisfetes. Aquesta tesi proposa contribucions per ajudar en aquests dos reptes, facilitant laboriosos passos manuals en el procés i ajudant als enginyers de disseny físic a obtenir millors resultats en menys temps. La primera contribució és el routing "under-the-cell", una proposta per connectar cel·les estàndard usant pins laterals en les capes de metall inferior de manera sistemàtica. L'objectiu és reduir la congestió en les capes de metall superior causades per l'ús de metall i vies, i així disminuir el nombre de violacions de regles de disseny. Per permetre la connexió lateral de cel·les, estenem una llibreria de cel·les estàndard amb dissenys que incorporen connexions laterals. També proposem modificacions locals al placement per permetre explotar aquest tipus de connexions més sovint. Els resultats experimentals mostren una reducció significativa en el nombre de pins, vies i nombre de violacions de regles de disseny, amb un impacte negligible en wirelength i timing. La segona contribució, desenvolupada en col·laboració amb eSilicon (una empresa capdavantera en disseny ASIC), és el desenvolupament de HiDaP, una eina de macro placement per a dissenys industrials actuals. La proposta segueix un procés multinivell per fer el floorplan de blocks jeràrquics, formats per macros i cel·les estàndard. Mitjançant la informació RTL disponible en la netlist, l'afinitat de dataflow entre els mòduls es modela i minimitza per trobar macro placements amb bones propietats de wirelength i timing. La proposta també incorpora la possibilitat de rebre input addicional de l'enginyer, com ara suggeriments de les posicions de les macros. Finalment, també usa mètodes espectrals i de forçes per guiar la cerca de floorplans. Els resultats experimentals mostren que els dissenys generats amb HiDaP són millors que els obtinguts per eines comercials capdavanteres de EDA. Els resultats també mostren que els dissenys presentats poden obtenir un wirelength similar i millor timing que macro placements obtinguts manualment, usats per fabricació. Alguns dissenys obtinguts per HiDaP s'han dut fins a timing-closure en una o dues rondes de modificacions incrementals per part d'enginyers de disseny físic. L'eina s'ha integrat en el procés de disseny de eSilicon i el seu desenvolupament continua més enllà de les aportacions a aquesta tesi.Postprint (published version
Algorithmic techniques for physical design : macro placement and under-the-cell routing
With the increase of chip component density and new manufacturability constraints imposed by modern technology nodes, the role of algorithms for electronic design automation is key to the successful implementation of integrated circuits. Two of the critical steps in the physical design flows are macro placement and ensuring all design rules are honored after timing closure.
This thesis proposes contributions to help in these stages, easing time-consuming manual steps and helping physical design engineers to obtain better layouts in reduced turnaround time.
The first contribution is under-the-cell routing, a proposal to systematically connect standard cell components via lateral pins in the lower metal layers. The aim is to reduce congestion in the upper metal layers caused by extra metal and vias, decreasing the number of design rule violations. To allow cells to connect by abutment, a standard cell library is enriched with instances containing lateral pins in a pre-selected sharing track. Algorithms are proposed to maximize the numbers of connections via lateral connection by mapping placed cell instances to layouts with lateral pins, and proposing local placement modifications to increase the opportunities for such connections. Experimental results show a significant decrease in the number of pins, vias, and in number of design rule violations, with negligible impact on wirelength and timing.
The second contribution, done in collaboration with eSilicon (a leading ASIC design company), is the creation of HiDaP, a macro placement tool for modern industrial designs. The proposed approach follows a multilevel scheme to floorplan hierarchical blocks, composed of macros and standard cells. By exploiting RTL information available in the netlist, the dataflow affinity between these blocks is modeled and minimized to find a macro placement with good wirelength and timing properties. The approach is further extended to allow additional engineer input, such as preferred macro locations, and also spectral and force methods to guide the floorplanning search.
Experimental results show that the layouts generated by HiDaP outperforms those obtained by a state-of-the-art EDA physical design software, with similar wirelength and better timing when compared to manually designed tape-out ready macro placements. Layouts obtained by HiDaP have successfully been brought to near timing closure with one to two rounds of small modifications by physical design engineers. HiDaP has been fully integrated in the design flows of the company and its development remains an ongoing effort.A causa de l'increment de la densitat de components en els xip i les noves restriccions de disseny imposades pels últims nodes de fabricació, el rol de l'algorísmia en l'automatització del disseny electrònic ha esdevingut clau per poder implementar circuits integrats. Dos dels passos crucials en el procés de disseny físic és el placement de macros i assegurar la correcció de les regles de disseny un cop les restriccions de timing del circuit són satisfetes. Aquesta tesi proposa contribucions per ajudar en aquests dos reptes, facilitant laboriosos passos manuals en el procés i ajudant als enginyers de disseny físic a obtenir millors resultats en menys temps. La primera contribució és el routing "under-the-cell", una proposta per connectar cel·les estàndard usant pins laterals en les capes de metall inferior de manera sistemàtica. L'objectiu és reduir la congestió en les capes de metall superior causades per l'ús de metall i vies, i així disminuir el nombre de violacions de regles de disseny. Per permetre la connexió lateral de cel·les, estenem una llibreria de cel·les estàndard amb dissenys que incorporen connexions laterals. També proposem modificacions locals al placement per permetre explotar aquest tipus de connexions més sovint. Els resultats experimentals mostren una reducció significativa en el nombre de pins, vies i nombre de violacions de regles de disseny, amb un impacte negligible en wirelength i timing. La segona contribució, desenvolupada en col·laboració amb eSilicon (una empresa capdavantera en disseny ASIC), és el desenvolupament de HiDaP, una eina de macro placement per a dissenys industrials actuals. La proposta segueix un procés multinivell per fer el floorplan de blocks jeràrquics, formats per macros i cel·les estàndard. Mitjançant la informació RTL disponible en la netlist, l'afinitat de dataflow entre els mòduls es modela i minimitza per trobar macro placements amb bones propietats de wirelength i timing. La proposta també incorpora la possibilitat de rebre input addicional de l'enginyer, com ara suggeriments de les posicions de les macros. Finalment, també usa mètodes espectrals i de forçes per guiar la cerca de floorplans. Els resultats experimentals mostren que els dissenys generats amb HiDaP són millors que els obtinguts per eines comercials capdavanteres de EDA. Els resultats també mostren que els dissenys presentats poden obtenir un wirelength similar i millor timing que macro placements obtinguts manualment, usats per fabricació. Alguns dissenys obtinguts per HiDaP s'han dut fins a timing-closure en una o dues rondes de modificacions incrementals per part d'enginyers de disseny físic. L'eina s'ha integrat en el procés de disseny de eSilicon i el seu desenvolupament continua més enllà de les aportacions a aquesta tesi
Algorithm to layout (ATL) systems for VLSI design
PhD ThesisThe complexities involved in custom VLSI design together with the
failure of CAD techniques to keep pace with advances in the fabrication
technology have resulted in a design bottleneck. Powerful tools are
required to exploit the processing potential offered by the densities now
available. Describing a system in a high level algorithmic notation
makes writing, understanding, modification, and verification of a design
description easier. It also removes some of the emphasis on the physical
issues of VLSI design, and focus attention on formulating a correct and
well structured design. This thesis examines how current trends in CAD
techniques might influence the evolution of advanced Algorithm To Layout
(ATL) systems. The envisaged features of an example system are
specified. Particular attention is given to the implementation of one
its features COPTS (Compilation Of Occam Programs To Schematics).
COPTS is capable of generating schematic diagrams from which an
actual layout can be derived. It takes a description written in a subset
of Occam and generates a high level schematic diagram depicting its
realisation as a VLSI system. This diagram provides the designer with
feedback on the relative placement and interconnection of the operators
used in the source code. It also gives a visual representation of the
parallelism defined in the Occam description. Such diagrams are a
valuable aid in documenting the implementation of a design.
Occam has also been selected as the input to the design system that
COPTS is a feature of. The choice of Occam was made on the assumption
that the most appropriate algorithmic notation for such a design system
will be a suitable high level programming language. This is in contrast
to current automated VLSI design systems, which typically use a hardware
des~ription language for input. These special purpose languages
currently concentrate on handling structural/behavioural information and
have limited ability to express algorithms. Using a language such as
Occam allows a designer to write a behavioural description which can be
compiled and executed as a simulator, or prototype, of the system. The
programmability introduced into the design process enables designers to
concentrate on a design's underlying algorithm. The choice of this
algorithm is the most crucial decision since it determines the
performance and area of the silicon implementation.
The thesis is divided into four sections, each of several chapters.
The first section considers VLSI design complexity, compares the expert
systems and silicon compilation approaches to tackling it, and examines
its parallels with software complexity. The second section reviews the
advantages of using a conventional programming language for VLSI system
descriptions. A number of alternative high level programming languages
are considered for application in VLSI design. The third section defines
the overall ATL system COPTS is envisaged to be part of, and considers
the schematic representation of Occam programs. The final section
presents a summary of the overall project and suggestions for future work
on realising the full ATL system
STRICT: a language and tool set for the design of very large scale integrated circuits
PhD ThesisAn essential requirement for the design of large VLSI circuits is a design methodology
which would allow the designer to overcome the complexity and correctness issues associated
with the building of such circuits.
We propose that many of the problems of the design of large circuits can be solved by using
a formal design notation based upon the functional programming paradigm, that embodies
design concepts that have been used extensively as the framework for software construction.
The design notation should permit parallel, sequential, and recursive decompositions
of a design into smaller components, and it should allow large circuits to be constructed
from simpler circuits that can be embedded in a design in a modular fashion. Consistency
checking should be provided as early as possible in a design. Such a methodology would
structure the design of a circuit in much the same way that procedures, classes, and control
structures may be used to structure large software systems.
However, such a design notation must be supported by tools which automatically check the
consistency of the design, if the methodology is to be practical. In principle, the methodology
should impose constraints upon circuit design to reduce errors and provide' correctness
by construction' . It should be possible to generate efficient and correct circuits, by providing
a route to a large variety of design tools commonly found in design systems: simulators,
automatic placement and routing tools, module generators, schematic capture tools, and
formal verification and synthesis tools
Vesyla-II: An Algorithm Library Development Tool for Synchoros VLSI Design Style
High-level synthesis (HLS) has been researched for decades and is still
limited to fast FPGA prototyping and algorithmic RTL generation. A feasible
end-to-end system-level synthesis solution has never been rigorously proven.
Modularity and composability are the keys to enabling such a system-level
synthesis framework that bridges the huge gap between system-level
specification and physical level design. It implies that 1) modules in each
abstraction level should be physically composable without any irregular glue
logic involved and 2) the cost of each module in each abstraction level is
accurately predictable. The ultimate reasons that limit how far the
conventional HLS can go are precisely that it cannot generate modular designs
that are physically composable and cannot accurately predict the cost of its
design. In this paper, we propose Vesyla, not as yet another HLS tool, but as a
synthesis tool that positions itself in a promising end-to-end synthesis
framework and preserving its ability to generate physically composable modular
design and to accurately predict its cost metrics. We present in the paper how
Vesyla is constructed focusing on the novel platform it targets and the
internal data structures that highlights the uniqueness of Vesyla. We also show
how Vesyla will be positioned in the end-to-end synchoros synthesis framework
called SiLago
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