A Technology Aware Magnetic QCA NCL-HDL Architecture

Magnetic Quantum Dot Cellular Automata (MQCA) have been recently proposed as an attractive implementation of QCA as a possible CMOS technology substitute. Marking a difference with respect to previous contributions, in this work we show that it is possible to develop and describe complex MQCA computational blocks strongly linking technology and having in mind a feasible realization. Thus, we propose a practicable clock structure for MQCA baptised "snake-clock", we stick to this while developing a system level Hardware Description Language (HDL) based description of an architectural block, and we suggest a delay insensitive Null Convention Logic (NCL) implementation for the magnetic case so that the "layout=timing" problem can be solved. Furthermore we include in our model aspects critically related to technology and real production, that is timing, power and layout, and we present the preliminary steps of our experiments, the results of which will be included in the architecture descriptio

Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

Bridging high-level synthesis to RTL technology libraries

The output of high-level synthesis typically consists of a netlist of generic RTL components and a state sequencing table. While module generators and logic synthesis tools can be used to map RTL components into standard cells or layout geometries, they cannot provide technology mapping into the data book libraries of functional RTL cells used commonly throughout the industrial design community. In this paper, we introduce an approach to implementing generic RTL components with technology-specific RTL library cells. This approach addresses the criticism of designers who feel that high-level synthesis tools should be used in conjunction with existing RTL data books. We describe how GENUS, a library of generic RTL components, is organized for use in high-level synthesis and how DTAS, a functional synthesis system, is used to map GENUS components into RTL library cells

VSS : a VHDL synthesis system

This report describes a register transfer synthesis system that allows a designer to interact with the design process. The designer can modify the compiled design by changing the input description, selecting optimization and mapping strategies, or graphically changing the generated design schematic. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization. The compilation process consists of two phases. First, a design composed of generic components is synthesized from the input description. Second, this design is translated into components from a particular library by a mapper and optimized by a logic optimizer. Redesign to new technologies can be accomplished by changing only the component library

A Survey of Digital Systems Curriculum and Pedagogy in Electrical and Computer Engineering Programs

Digital Systems is one of the basic foundational courses in Electrical and Computer Engineering. One of the challenges in designing and modifying the curriculum for the course is the fast pace of technology change in the area. TTL chips that were in vogue with students building physical circuits, have given way to new paradigms like FPGA based synthesis with hardware description languages such as VHDL. However, updating a course is not as simple as just changing the book, and changing the syllabus. A large amount of work needs to be done in terms of selecting the book that will accommodate the course, the device that should be used, the laboratory content, and even how much time needs to be dedicated for every topic. All these issues, and many more makes it hard to take the decision of updating the course. For that reason, this paper surveys the pedagogy and methodology that is used to teach the digital systems curriculum at different universities. The goal is that it will serve as a resource for faculty looking to update or revamp their digital systems curricula. Within the document they will find a comparative study by electrical and computer engineering program, a list of textbooks, and the devices most commonly used.Cockrell School of Engineerin

Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders

The quantum dot Cellular Automata (QCA) is an emerging nanotechnology that has gained significant research interest in recent years. Extremely small feature sizes, ultralow power consumption, and high clock frequency make QCA a potentially attractive solution for implementing computing architectures at the nanoscale. To be considered as a suitable CMOS substitute, the QCA technology must be able to implement complex real-time applications with affordable complexity. Low density parity check (LDPC) decoding is one of such applications. The core of LDPC decoding lies in the check node (CN) processing element which executes actual decoding algorithm and contributes toward overall performance and complexity of the LDPC decoder. This study presents a novel QCA architecture for partial parallel, layered LDPC check node. The CN executes Normalized Min Sum decoding algorithm and is flexible to support CN degree dc up to 20. The CN is constructed using a VHDL behavioral model of QCA elementary circuits which provides a hierarchical bottom up approach to evaluate the logical behavior, area, and power dissipation of the whole design. Performance evaluations are reported for the two main implementations of QCA i.e. molecular and magneti

A Fast and Accurate Cost Model for FPGA Design Space Exploration in HPC Applications

Heterogeneous High-Performance Computing (HPC) platforms present a significant programming challenge, especially because the key users of HPC resources are scientists, not parallel programmers. We contend that compiler technology has to evolve to automatically create the best program variant by transforming a given original program. We have developed a novel methodology based on type transformations for generating correct-by-construction design variants, and an associated light-weight cost model for evaluating these variants for implementation on FPGAs. In this paper we present a key enabler of our approach, the cost model. We discuss how we are able to quickly derive accurate estimates of performance and resource-utilization from the design’s representation in our intermediate language. We show results confirming the accuracy of our cost model by testing it on three different scientific kernels. We conclude with a case-study that compares a solution generated by our framework with one from a conventional high-level synthesis tool, showing better performance and power-efficiency using our cost model based approach