Deductive Fault Simulation Technique for Asynchronous Circuits

Fault simulator for acpASC needs to deal with hazards, oscillations and races. The simplest algorithm for simulating faults is the serial fault simulation technique which was successfully used for the acpASC. Faster fault simulation techniques, for example deductive fault simulation, was previously used for the combinational and synchronous sequential circuits only. In this paper a deductive fault simulator for the stuck-at faults of acSI acpASC is presented. An algorithm for the propagation of the fault lists is proposed which can deal with the complex gates of the acpASC. The implemented deductive fault simulator was tested using acSI benchmark circuits. The experimental results show significant reduction of the computation time and negligible increase of the memory requirements in comparison with the serial fault simulation technique

Gate Delay Fault Test Generation for Non-Scan Circuits

This article presents a technique for the extension of delay fault test pattern generation to synchronous sequential circuits without making use of scan techniques. The technique relies on the coupling of TDgen, a robust combinational test pattern generator for delay faults, and SEMILET, a sequential test pattern generator for several static fault models. The approach uses a forward propagation-backward justification technique: The test pattern generation is started at the fault location, and after successful ¿local¿ test generation fault effect propagation is performed and finally a synchronising sequence to the required state is computed. The algorithm is complete for a robust gate delay fault model, which means that for every testable fault a test will be generated, assuming sufficient time. Experimental results for the ISCAS'89 benchmarks are presented in this pape

A Signal Distribution Network for Sequential Quantum-dot Cellular Automata Systems

The authors describe a signal distribution network for sequential systems constructed using the Quantum-dot Cellular Automata (QCA) computing paradigm. This network promises to enable the construction of arbitrarily complex QCA sequential systems in which all wire crossings are performed using nearest neighbor interactions, which will improve the thermal behavior of QCA systems as well as their resistance to stray charge and fabrication imperfections. The new sequential signal distribution network is demonstrated by the complete design and simulation of a two-bit counter, a three-bit counter, and a pattern detection circuit

Redundant Logic Insertion and Fault Tolerance Improvement in Combinational Circuits

This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit as is the case with conventional redundancy techniques. In this context, it is discussed how to estimate the fault masking capability of a combinational circuit using the truth-cum-fault enumeration table, and then it is shown how to identify the logic that can introduced to add redundancy into the original circuit without affecting its native functionality and with the aim of improving its fault tolerance though this would involve some trade-off in the design metrics. However, care should be taken while introducing redundant logic since redundant logic insertion may give rise to new internal nodes and faults on those may impact the fault tolerance of the resulting circuit. The combinational circuit that is considered and its redundant counterparts are all implemented in semi-custom design style using a 32/28nm CMOS digital cell library and their respective design metrics and fault tolerances are compared

Single-Event Upset Analysis and Protection in High Speed Circuits

The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a single event upset (SEU) caused by particle strike on the internal nodes of a flip-flo

Sequential circuit design in quantum-dot cellular automata

In this work we present a novel probabilistic modeling scheme for sequential circuit design in quantum-dot cellular automata(QCA) technology. Clocked QCA circuits possess an inherent direction for flow of information which can be effectively modeled using Bayesian networks (BN). In sequential circuit design this presents a problem due to the presence of feedback cycles since BN are direct acyclic graphs (DAG). The model presented in this work can be constructed from a logic design layout in QCA and is shown to be a dynamic Bayesian Network (DBN). DBN are very powerful in modeling higher order spatial and temporal correlations that are present in most of the sequential circuits. The attractive feature of this graphical probabilistic model is that that it not only makes the dependency relationships amongst node explicit, but it also serves as a computational mechanism for probabilistic inference. We analyze our work by modeling clocked QCA circuits for SR F/F, JK F/F and RAM designs

On testing VLSI chips for the big Viterbi decoder

A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature