Code Generation From Hierarchical Concurrency Specifications

Rapport interne.This paper explains how executable Java code is generated from hierarchical specifications in the Concurrency Factory specification and verification environment. Besides the ability to generate executable code from verified, abstract concurrency specifications, the paper's main contributions include: (1) new solutions to the well-known input/output guard-scheduling problem in the context of hierarchically configured concurrent systems; (2) code-generation algorithms that produce both thread-based Java code and distributed ADA code; (3) the use of the Concurrency Factory itself to verify an abstraction of each generated code module; in this sense, the Factory is self-verifying; and, finally, (4) a report on our experience in executing the generated code for simulation and debugging purposes in the case of the Rether real-time ethernet protocol

Schedulability analysis and automated implementation of real-time object-oriented design models

There is a growing interest in adopting object technologies for the development of real-time systems. Several commercial tools, currently available, provide object-oriented modeling and design support for real-time systems. While these products provide many useful facilities, such as visualization tools and automatic code generation, they are all weak in addressing the central characteristic of real-time system design, i.e., providing support for a designer to reason about timeliness properties. We believe an approach that integrates the advancements in both object modeling and design methods, and real-time scheduling theory is the key to successful use of object technology for real-time software. We propose a methodology based on this idea for uni-processor multi-threaded environments. Specifically, given an application design model and end-to-end timing requirements, we synthesize a feasible implementation model using a built-in schedulability analysis tool. The synthesis process is supported by automatic code generation that can take the application design model and the synthesized implementation model and generate code for the target platform. In this thesis, I have designed and implemented some of the key components to support this methodology. First, I have developed a schedulability test that determines whether a particular implementation model satisfies the real-time requirements of an application. This can be used during the automatic synthesis process. Second, I have developed an initial implementation supporting automatic code generation, which takes textual specifications of the application design model and a synthesized implementation model, and automatically generates executable code for i

Automatic generation of SDL specifications from timed MSCs

The integration of Formal Description Techniques (FDTs) in the software process enables formal validation, translation, synthesis and code generation. Message Sequence Charts (MSC) and Specification and Description Language (SDL) are two formal languages, widely used in the telecommunication industry. Generally MSC is used for the behavioral requirement specification, while SDL is used for the detailed design specification. The transition from the requirement specification to the design specification is usually performed manually; and the design has to be validated against the requirement specification. In a previous research work, researchers from the telesoft group at Concordia University devised an approach for generating SDL specifications from MSC specifications with a given target architecture. It guarantees correctness of the design, and consistency between the SDL specification and the MSC specification. The need for validation has been eliminated. Time concepts have been introduced in MSC-2000, which enables real-time requirements to be specified in MSC. Building on the existing framework, this thesis presents a new approach for translating MSCs with real-time requirements into SDL specifications. We analyzed and classified different types of time constraints and measurements. New algorithms for analyzing MSC specifications and generating SDL code were devised. We also built the tool and experimented with case studies to prove the feasibility of our approach

Re-factoring based program repair applied to programming assignments

Automated program repair has been used to provide feedback for incorrect student programming assignments, since program repair captures the code modification needed to make a given buggy program pass a given test-suite. Existing student feedback generation techniques are limited because they either require manual effort in the form of providing an error model, or require a large number of correct student submissions to learn from, or suffer from lack of scalability and accuracy. In this work, we propose a fully automated approach for generating student program repairs in real-time. This is achieved by first re-factoring all available correct solutions to semantically equivalent solutions. Given an incorrect program, we match the program with the closest matching refactored program based on its control flow structure. Subsequently, we infer the input-output specifications of the incorrect program's basic blocks from the executions of the correct program's aligned basic blocks. Finally, these specifications are used to modify the blocks of the incorrect program via search-based synthesis. Our dataset consists of almost 1,800 real-life incorrect Python program submissions from 361 students for an introductory programming course at a large public university. Our experimental results suggest that our method is more effective and efficient than recently proposed feedback generation approaches. About 30% of the patches produced by our tool Refactory are smaller than those produced by the state-of-art tool Clara, and can be produced given fewer correct solutions (often a single correct solution) and in a shorter time. We opine that our method is applicable not only to programming assignments, and could be seen as a general-purpose program repair method that can achieve good results with just a single correct reference solution

Using formal methods to support testing

Formal methods and testing are two important approaches that assist in the development of high quality software. While traditionally these approaches have been seen as rivals, in recent years a new consensus has developed in which they are seen as complementary. This article reviews the state of the art regarding ways in which the presence of a formal specification can be used to assist testing

Validate implementation correctness using simulation: the TASTE approach

High-integrity systems operate in hostile environment and must guarantee a continuous operational state, even if unexpected events happen. In addition, these systems have stringent requirements that must be validated and correctly translated from high-level specifications down to code. All these constraints make the overall development process more time-consuming. This becomes especially complex because the number of system functions keeps increasing over the years. As a result, engineers must validate system implementation and check that its execution conforms to the specifications. To do so, a traditional approach consists in a manual instrumentation of the implementation code to trace system activity while operating. However, this might be error-prone because modifications are not automatic and still made manually. Furthermore, such modifications may have an impact on the actual behavior of the system. In this paper, we present an approach to validate a system implementation by comparing execution against simulation. In that purpose, we adapt TASTE, a set of tools that eases system development by automating each step as much as possible. In particular, TASTE automates system implementation from functional (system functions description with their properties – period, deadline, priority, etc.) and deployment(processors, buses, devices to be used) models. We tailored this tool-chain to create traces during system execution. Generated output shows activation time of each task, usage of communication ports (size of the queues, instant of events pushed/pulled, etc.) and other relevant execution metrics to be monitored. As a consequence, system engineers can check implementation correctness by comparing simulation and execution metrics

An environment for object-oriented real-time system design

A concise object-oriented method for the development of real-time systems has been composed. Hardware components are modelled by (software) base objects; base objects are controlled by a hierarchy of coordinator objects, expressed in an organizational diagram. The behaviour of objects is specified by state transition diagrams. This approach considerably promotes requirements analysis and communication with the customer. A CASE tool has been constructed with diagram editors for graphical specifications of real-time systems. The tool can generate executable code for PLCs from these graphical specifications; reuse of previous results is supported by the repository function of the tool. Experiences attained in practice with method and tool show that time spent in system testing and installation is reduced considerabl