Economic and environmental impacts of the energy source for the utility production system in the HDA process

The well-known benchmark process for hydrodealkylation of toluene (HDA) to produce benzene is revisited in a multi-objective approach for identifying environmentally friendly and cost-effective operation solutions. The paper begins with the presentation of the numerical tools used in this work, i.e., a multi-objective genetic algorithm and a Multiple Choice Decision Making procedure. Then, two studies related to the energy source involved in the utility production system (UPS), either fuel oil or natural gas, of the HDA process are carried out. In each case, a multi-objective optimization problem based on the minimization of the total annual cost of the process and of five environmental burdens, that are Global Warming Potential, Acidification Potential, Photochemical Ozone Creation Potential, Human Toxicity Potential and Eutrophication Potential, is solved and the best solution is identified by use of Multiple Choice Decision Making procedures. An assessment of the respective contribution of the HDA process and the UPS towards environmental impacts on the one hand, and of the environmental impacts generated by the main equipment items of the HDA process on the other hand is then performed to compare both solutions. This ‘‘gate-to-gate’’ environmental study is then enlarged by implementing a ‘‘cradle-togate’’ Life Cycle Assessment (LCA), for accounting of emission inventory and extraction. The use of a natural gas turbine, less economically efficient, turns out to be a more attractive alternative to meet the societal expectations concerning environment preservation and sustainable development

Design of multimedia processor based on metric computation

Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-time constraints of those media applications have taxing demands on today's processor performances with low cost, low power and reduced design delay. To satisfy those challenges, a fast and efficient strategy consists in upgrading a low cost general purpose processor core. This approach is based on the personalization of a general RISC processor core according the target multimedia application requirements. Thus, if the extra cost is justified, the general purpose processor GPP core can be enforced with instruction level coprocessors, coarse grain dedicated hardware, ad hoc memories or new GPP cores. In this way the final design solution is tailored to the application requirements. The proposed approach is based on three main steps: the first one is the analysis of the targeted application using efficient metrics. The second step is the selection of the appropriate architecture template according to the first step results and recommendations. The third step is the architecture generation. This approach is experimented using various image and video algorithms showing its feasibility

CESEC Chair – Training Embedded System Architects for the Critical Systems Domain

Increasing complexity and interactions across scientific and tech- nological domains in the engineering of critical systems calls for new pedagogical approach. In this paper, we introduce the CESEC teaching chair. This chair aims at supporting new integrative ap- proach for the initial training of engineer and master curriculum to three engineering school in Toulouse: ISAE, INSA Toulouse and INP ENSEEIHT. It is supported by the EADS Corporate Foundation. In this paper, we highlight the rationale for this chair: need for sys- tem architect with strong foundations on technical domains appli- cable to the aerospace industry. We then introduce the ideal profile for this architect and the various pedagogical approaches imple- mented to reach this objective

Special Session on Industry 4.0

No abstract available

Trojans in Early Design Steps—An Emerging Threat

Hardware Trojans inserted by malicious foundries during integrated circuit manufacturing have received substantial attention in recent years. In this paper, we focus on a different type of hardware Trojan threats: attacks in the early steps of design process. We show that third-party intellectual property cores and CAD tools constitute realistic attack surfaces and that even system specification can be targeted by adversaries. We discuss the devastating damage potential of such attacks, the applicable countermeasures against them and their deficiencies

Hardware/Software Codesign

The current state of the art technology in integrated circuits allows the incorporation of multiple processor cores and memory arrays, in addition to application specific hardware, on a single substrate. As silicon technology has become more advanced, allowing the implementation of more complex designs, systems have begun to incorporate considerable amounts of embedded software [3]. Thus it becomes increasingly necessary for the system designers to have knowledge on both hardware and software to make efficient design tradeoffs. This is where hardware/software codesign comes into existence

Exploiting the Temporal Logic Hierarchy and the Non-Confluence Property for Efficient LTL Synthesis

The classic approaches to synthesize a reactive system from a linear temporal logic (LTL) specification first translate the given LTL formula to an equivalent omega-automaton and then compute a winning strategy for the corresponding omega-regular game. To this end, the obtained omega-automata have to be (pseudo)-determinized where typically a variant of Safra's determinization procedure is used. In this paper, we show that this determinization step can be significantly improved for tool implementations by replacing Safra's determinization by simpler determinization procedures. In particular, we exploit (1) the temporal logic hierarchy that corresponds to the well-known automata hierarchy consisting of safety, liveness, Buechi, and co-Buechi automata as well as their boolean closures, (2) the non-confluence property of omega-automata that result from certain translations of LTL formulas, and (3) symbolic implementations of determinization procedures for the Rabin-Scott and the Miyano-Hayashi breakpoint construction. In particular, we present convincing experimental results that demonstrate the practical applicability of our new synthesis procedure