Design of a Class-D Audio Amplifier With Analog Volume Control for Mobile Applications

A class-D audio amplifier with analog volume control (AVC) section and driver section for wireless and portable applications is proposed in this paper. The analog volume control section, including an integrator, an analog MUX, and a programmable gain amplifier (PGA) is implemented with three analog inputs (Audio, Voice, FM). For driver section, including a ramp generator, a comparator, a level shifter and a gate driver is designed to obtain a low distortion and a highefficiency. Designed with 0.18 um 1P6M CMOS technology, the class-D audio amplifier with analog volume control achieves a total root-mean-square (RMS) output power of 0.5W, a total harmonic distortion plus noise (THD+N) at the 8-Ω load less than 0.06%, and a power efficiency of 89.9% with a total area of 1.74mm2

A Class-AB/D Audio Power Amplifier for Mobile Applications Integrated Into a 2.5G/3G Baseband Processor

A filterless class-AB/D audio power amplifier integrated into a feature-rich 2.5G/3G baseband processor in standard 65-nm CMOS technology is designed for direct battery hookup in mobile phone applications. Circuit techniques are used to overcome the voltage limitations of standard MOS transistors for operation at voltage levels of 2.5-4.8 V. Both amplifiers can drive more than 650 mW into an 8-Omega load with maximum distortion levels of 1% and 5% for class-D and class-AB, respectively, all from a 3.6-V power supply. The achieved power-supply-rejection ratios are 72 and 84 dB, respectively. The mono implementation of both amplifiers together is 0.44 mm(2)

Laboratory implementations of PMSM drive in hybrid electric vehicles applications

Field Programmable Gate Arrays (FPGAs) are one of the today\u27s most successful technologies for developing systems that require real time operation and providing additional flexibility to the designer. This research is focused on developing a control board for a permanent magnet synchronous machine (PMSM) using an FPGA module. The board is configured for individual use of an FPGA, digital signal processor (DSP) or in combination to control the PMSM by generating the required Pulse Width Modulator (PWM) to the inverter in order to drive and control the speed of the PMSM. Since, the exact rotor position and speed are required to control the motor; a useful method is developed digitally and implemented in the FPGA hardware module. The speed observer (SO), in which the Hall effect signals were used to calculate the speed and the angle of the rotor. In this thesis, three different techniques of PWM generation were developed and combined with rotor position and speed method. The project is implemented in Altera FPGA using Quartus II software V11.0 with VHDL as the supporting language. The design achieved high performance and accuracy of the detection estimation and control scheme for the Permanent Magnet Synchronous Machine. Error and design analysis has been done also --Abstract, page iii

IMPLEMENTATION OF AUTONOMOUS BALL FEEDER MOBILE ROBOT

The objective of the project is to design and implement autonomous ball feeder mobile robot. The robot will be able to feed the ball into the outer torch automatically. The purpose of designing the robot is to enter the ROBOCON competition organized by SIRIM. This is the first participation of University Technology PETRONAS in ROBOCON competition since it is an annually competition from 2002. Without any past experience on building a robot, the Electrical & Electronic department has given the author challenges to build an autonomous robot base on certain constrains restricted by the rules stated by the organizer. The robot will be bigger in size and capable to carry heavier loads. The scope of the study will be mainly on the design and implementation of the robot from scratch or little knowledge. The study will be handled part by part from researching on the whole part of the robot until the implementation of the workable robot. The robot implementation can be divided into two main sections which is hardware and controller part ofthe robot. In the discussion part, all the robot implementation will be discussed in more detail as to make sure the objective of the project can be achieved successfully. The problem and the solution for the problem will also be discussed base on the student point of view. Before ending the chapter, some recommendation has been suggested for further improvement for the next ROBOCON team members. The suggestions made are base on the current available technology and also the experience gain by the author through out this design project. To conclude the thesis paper, the conclusion will wrap up the whole findings in a general view

Implementation of Grid Computing for Cryptosystem (RSA)

RSA cipher is of the asymmetric encryption technique that is widely used today over the internet and a large network environment. The RSA algorithm can be used for both public key encryption and digital signatures. Its security isbased on the difficulty of factoring large integers. Current industry practice is use larger bits as example 512 bit encryption which is computationally intensive as it requires a large memory size and bigger processor speed to achieve relatively speed on time taken to cipher or encrypt data. However, withthe emerging of grid computing architecture, it is believe that processing time to process RSA algorithm can be reduce as it use more resource together with a parallel computing element. One objective ofthis project is to perform a small scale study in order to set up a grid computing that can support faster computation ofRSA Algorithm. Apart from that, the other objective is to implement a suitable grid computing architecture that is able to support parallel processing. Lastly the project has the objective to deploy and a grid computing facility that will beuse as a test bed for RSA algorithm Methodology used for the development is Rapid Application Development (RAD) as it will allow for fast development with a series of testing and prototyping. i

Palmo : a novel pulsed based signal processing technique for programmable mixed-signal VLSI

In this thesis a new signal processing technique is presented. This technique exploits the use of pulses as the signalling mechanism. This Palmo 1 signalling method applied to signal processing is novel, combining the advantages of both digital and analogue techniques. Pulsed signals are robust, inherently low-power, easily regenerated, and easily distributed across and between chips. The Palmo cells used to perform analogue operations on the pulsed signals are compact, fast, simple and programmable

MOBILE ROBOTS: OBSTACLE AVOIDANCE AND MANUVERING

The objective of the project is to design and implement a mobile robot. The robot will be able to avoid obstacles and have its own decision making capability. It will be a part of the preparation for the department of Electrical Electronics Engineering University Teknoiogi Petronas for various activities which require robotics design participation. As one of the final year electrical electronics student I have been given the chance to be part of the path finding. The scope of the study will be mainly on the design and implementation of the robot from scratch or little knowledge. The study will be handled part by part for components needed for the robot. First will be the structure of the robot. Next the mobility and drive circuit will be design to enable the robot to be mobile. Sensors will be put in place so that the robot is able to "feel" and "see" it's surrounding. When this is done a "brain" or microcontroller will be put in place so that it is able to control itself and make simple decision. The methodology or approach can be divided into software and hardware. Basically the same methodology will be use again and again in the module design process. Finally the parts will be integrated as one mobile robot. This will become the final robot. In the discussion part, the findings are being discussed in detail. The problem and the solution for the problem is being discussed base on the student point of view. The reader might get the idea on the limitations of a mobile robot as the size and weight increases. These are the factors that are becoming the bottle neck in this design project. Before ending the chapter, some recommendation has been suggested for further improvement by future robotics builder. The suggestions are made base on ^q current available technology and also the experience gain by the student through out this design project

Homogeneous and heterogeneous MPSoC architectures with network-on-chip connectivity for low-power and real-time multimedia signal processing

Two multiprocessor system-on-chip (MPSoC) architectures are proposed and compared in the paper with reference to audio and video processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32-bit RISC core enhanced by a 64-bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneous-tile topology with on-chip distributed memory resources; the tiles act as application specific processors supporting a different class of algorithms. In both architectures, the multiple tiles are interconnected by a network-on-chip (NoC) infrastructure, through network interfaces and routers, which allows parallel operations of the multiple tiles. The functional performances and the implementation complexity of the NoC-based MPSoC architectures are assessed by synthesis results in submicron CMOS technology. Among the large set of supported algorithms, two case studies are considered: the real-time implementation of an H.264/MPEG AVC video codec and of a low-distortion digital audio amplifier. The heterogeneous architecture ensures a higher power efficiency and a smaller area occupation and is more suited for low-power multimedia processing, such as in mobile devices. The homogeneous scheme allows for a higher flexibility and easier system scalability and is more suited for general-purpose DSP tasks in power-supplied devices