Delay Extraction based Macromodeling with Parallel Processing for Efficient Simulation of High Speed Distributed Networks

This thesis attempts to address the computational demands of accurate modeling of high speed distributed networks such as interconnect networks and power distribution networks. In order to do so, two different approaches towards modeling of high speed distributed networks are considered. One approach deals with cases where the physical characteristics of the network are not known and the network is characterized by its frequency domain tabulated data. Such examples include long interconnect networks described by their Y parameter data. For this class of problems, a novel delay extraction based IFFT algorithm has been developed for accurate transient response simulation. The other modeling approach is based on a detailed knowledge of the physical and electrical characteristics of the network and assuming a quasi transverse mode of propagation of the electromagnetic wave through the network. Such problems may include two dimensional (2D) and three dimensional (3D) power distribution networks with known geometry and materials. For this class of problem, a delay extraction based macromodeling approaches is proposed which has been found to be able to capture the distributed effects of the network resulting in more compact and accurate simulation compared to the state-of-the-art quasi-static lumped models. Furthermore, waveform relaxation based algorithms for parallel simulations of large interconnect networks and 2D power distribution networks is also presented. A key contribution of this body of work is the identification of naturally parallelizable and convergent iterative techniques that can divide the computational costs of solving such large macromodels over a multi-core hardware

High-Performance Computing for the Electromagnetic Modeling and Simulation of Interconnects

The electromagnetic modeling of packages and interconnects plays a very important role in the design of high-speed digital circuits, and is most efficiently performed by using computer-aided design algorithms. In recent years, packaging has become a critical area in the design of high-speed communication systems and fast computers, and the importance of the software support for their development has increased accordingly. Throughout this project, our efforts have focused on the development of modeling and simulation techniques and algorithms that permit the fast computation of the electrical parameters of interconnects and the efficient simulation of their electrical performance

Development of Measurement-based Time-domain Models and its Application to Wafer Level Packaging

In today's semiconductor-based computer and communication technology, system performance is determined primarily by two factors, namely on-chip and off-chip operating frequency. In this dissertation, time-domain measurement-based methods that enable gigabit data transmission in both the IC and package have been proposed using Time-Domain Reflectometry (TDR) equipment. For the evaluation of the time-domain measurement-based method, a wafer level package test vehicle was designed, fabricated and characterized using the proposed measurement-based methods. Electrical issues associated with gigabit data transmission using the wafer-level package test vehicle were investigated. The test vehicle consisted of two board transmission lines, one silicon transmission line, and solder bumps with 50um diameter and 100um pitch. In this dissertation, 1) the frequency-dependent characteristic impedance and propagation constant of the transmission lines were extracted from TDR measurements. 2) Non-physical RLGC models for transmission lines were developed from the transient behavior for the simulation of the extracted characteristic impedance and propagation constant. 3) the solder bumps with 50um diameter and 100um pitch were analytically modeled. Then, the effect of the assembled wafer-level package, silicon substrate and board material, and material interfaces on gigabit data transmission were discussed using the wafer-level package test vehicle. Finally, design recommendations for the wafer-level package on integrated board were proposed for gigabit data transmission in both the IC and package.Ph.D.Committee Chair: Swaminathan, Madhavan; Committee Member: Kenney, J. Stevenson; Committee Member: Peterson, Andrew F.; Committee Member: Tummala, Rao R.; Committee Member: Wong, C. P

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Department of Electrical EngineeringThese days, the pulse width modulation (PWM) inverter-fed drive is commonly used for the motor drive systems. As the switching speed increases, the fast rising and falling transients generate significant electromagnetic (EM) emission in the system, which can affect to other integrated devices. Since there are hundreds of turns in the winding structure, the ac motor operates as one of the main EM noise path in the system. Therefore, the study of the high-frequency characteristic for the ac motor, and design method of the ac motor to be robust against the electromagnetic interference (EMI) issues are getting important. In this thesis, an electromagnetic compatibility (EMC) aware design method of an ac motor is presented by the network parameter analysis of the input impedance including the high-frequency coupling elements. To estimate the high-frequency characteristics of the ac motor, an equivalent circuit modeling method is presented. From the wide-frequency response of the windings, the frequency-dependent per-unit-length (PUL) transmission line (RLGC) parameters are extracted, and a PUL equivalent circuit model is constructed by investigating the frequency characteristics of the RLGC parameters. Moreover, the shunt admittance model describing the stepwise decrease of capacitance is developed by applying Debye and Lorentz model. To verify the availability of the constructed equivalent circuit model, the input impedance and the transfer impedance for the entire length of the phase line are compared with the measurement. The input impedances matched with high accuracy over the wide-frequency region. After establishing the equivalent circuit model for the phase winding structure of the ac motor, an extraction method of the six-port multi-network parameters for all the three-phase windings is presented because the phase-to-phase coupling may conduct EM noise by the excitation from the other phases. Under the assumption of a symmetric structure, the multi-port network parameters are obtained by the conversion of two-port mixed-mode network parameters, which include the relations between common-mode (CM) and differential-mode (DM). The method simplifies the calculation to extract the impedance parameters of the three-phase winding structure without the full six-port measurement. Furthermore, the phase-to-phase coupling can be estimated by the converted network matrices. In addition, the method is extended to the shaft structure to capture the winding-to-shaft coupling characteristics in the ac motor. The extracted impedance parameters include the coupling effects between CM noise, DM noise, and the end-sides of the shaft. For verification, the calculated impedances are compared with the measured input impedance for the phase line. The suggested multi-port network parameter extraction method can be used to estimate the EM coupling parameters between any structure part of the ac motor, CM noise, and DM noise by simple two-port mixed-mode network conversion. Using the equivalent circuit model and multi-port network analysis method, a design method of the EMC-aware ac motor is proposed by investigating the CM input impedance of the phase windings. The most effective coupling elements of the input impedance are defined with comparing the presented PUL equivalent circuit. Moreover, the electromagnetic (EM) field simulation including all the conductors of the ac motor is performed for the models of the separated parts of the ac motor structure. The multi-port networks are constructed from the EM simulation data, and the input impedance of the full-winding structure is extracted by the calculation of the network parameter matrices. The change of the input impedances due to the variation of the design parameters is studied through parametric analysis of the automated design code. By comparing the extracted input impedances for the different ac motor models, the EMC design method for the ac motor is established with considering the core loss and torque ripple together. To verify the design method, the CM current is measured for the redesigned ac motors when the motors are operating in the drive system. The result shows that the CM current is reduced up to 10dB by adjusting the motor design parameter. Consequently, the proposed method can predict the input impedance of the motor with high accuracy in the motor design stage before manufacturing. In addition, the proposed method can be applied to any type of ac motors and various design parameters.clos

Advanced modelling and design considerations for interconnects in ultra- low power digital system

PhD ThesisAs Very Large Scale Integration (VLSI) is progressing in very Deep submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption for advanced System-on- Chip (SoC)s. However, the growing complexity of interconnects behaviour presents a challenge for their adequate modelling, whereby conventional circuit theoretic approaches cannot provide sufficient accuracy. During the last decades, fractional differential calculus has been successfully applied to modelling certain classes of dynamical systems while keeping complexity of the models under acceptable bounds. For example, fractional calculus can help capturing inherent physical effects in electrical networks in a compact form, without following conventional assumptions about linearization of non-linear interconnect components. This thesis tackles the problem of interconnect modelling in its generality to simulate a wide range of interconnection configurations, its capacity to emulate irregular circuit elements and its simplicity in the form of responsible approximation. This includes modelling and analysing interconnections considering their irregular components to add more flexibility and freedom for design. The aim is to achieve the simplest adaptable model with the highest possible accuracy. Thus, the proposed model can be used for fast computer simulation of interconnection behaviour. In addition, this thesis proposes a low power circuit for driving a global interconnect at voltages close to the noise level. As a result, the proposed circuit demonstrates a promising solution to address the energy and performance issues related to scaling effects on interconnects along with soft errors that can be caused by neutron particles. The major contributions of this thesis are twofold. Firstly, in order to address Ultra-Low Power (ULP) design limitations, a novel driver scheme has been configured. This scheme uses a bootstrap circuitry which boosts the driver’s ability to drive a long interconnect with an important feedback feature in it. Hence, this approach achieves two objectives: improving performance and mitigating power consumption. Those achievements are essential in designing ULP circuits along with occupying a smaller footprint and being immune to noise, observed in this design as well. These have been verified by comparing the proposed design to the previous and traditional circuits using a simulation tool. Additionally, the boosting based approach has been shown beneficial in mitigating the effects of single event upset (SEU)s, which are known to affect DSM circuits working under low voltages. Secondly, the CMOS circuit driving a distributed RLC load has been brought in its analysis into the fractional order domain. This model will make the on-chip interconnect structure easy to adjust by including the effect of fractional orders on the interconnect timing, which has not been considered before. A second-order model for the transfer functions of the proposed general structure is derived, keeping the complexity associated with second-order models for this class of circuits at a minimum. The approach here attaches an important trait of robustness to the circuit design procedure; namely, by simply adjusting the fractional order we can avoid modifying the circuit components. This can also be used to optimise the estimation of the system’s delay for a broad range of frequencies, particularly at the beginning of the design flow, when computational speed is of paramount importance.Iraqi Ministry of Higher Education and Scientific Researc

Automated parametrical antenna modelling for ambient assisted living applications

In this paper a parametric modeling technique for a fast polynomial extraction of the physically relevant parameters of inductively coupled RFID/NFC (radio frequency identification/near field communication) antennas is presented. The polynomial model equations are obtained by means of a three-step procedure: first, full Partial Element Equivalent Circuit (PEEC) antenna models are determined by means of a number of parametric simulations within the input parameter range of a certain antenna class. Based on these models, the RLC antenna parameters are extracted in a subsequent model reduction step. Employing these parameters, polynomial equations describing the antenna parameter with respect to (w.r.t.) the overall antenna input parameter range are extracted by means of polynomial interpolation and approximation of the change of the polynomials' coefficients. The described approach is compared to the results of a reference PEEC solver with regard to accuracy and computation effort

Advanced Electromagnetic Numerical Modeling Techniques for Various Periodic and Quasi-Periodic Systems

This dissertation is mainly concerned with several advanced electromagnetic modeling techniques for practical complex systems, which involve periodic analyses. The focus is to reveal the physics of the electromagnetic wave interaction with the complex structures, and also to arrive at improved computational algorithms. This dissertation consists of three self-contained parts, each discussing one modeling technique. Examples presented in this dissertation include (a) an analysis of conductor surface-roughness effects, (b) a novel model for vertical interconnects (vias) and (c) a leaky-wave study of a Fabry-Perot resonant cavity antenna. The first part investigates conductor surface roughness effects for stripline. An equivalent rough-surface-impedance is extracted using a periodic full-wave analysis and is then used for the modification of the transmission line per-unit-length parameter. The second part proposes a semi-analytical analysis for massively-coupled vias with arbitrarily-shaped antipads, based on the reciprocity theorem. The use of reciprocity yields simple design formulas and is seen to greatly improve the computational efficiency, due to the fast-converging mode-matching calculation. The third part presents a leaky-wave study of a Fabry-Perot cavity antenna made from a patch array. The patch current densities are calculated using the array scanning method. Based on this, a "leaky-wave current" is defined and calculated using residue integration. In addition, the radiation properties of a large finite-size array (truncation effects) are evaluated. All three proposed models are verified by full-wave simulations and/or measurements. Numerical results prove the effectiveness and accuracy of these models.Electrical and Computer Engineering, Department o

Ku band rotary traveling-wave voltage controlled oscillator

Voltage-controlled oscillator (VCO) plays a key role in determination of the link budget of wireless communication, and consequently the performance of the transceiver. Lowering the noise contribution from the VCO to the entire system is always challenging and remains the active research area. Motivated by high demands for the low-phase noise, low-power consumption VCO in the application of 5G, radar-sensing system, implantable device, to name a few, this research focused on the design of a rotary travelling-wave oscillator (RTWO). A power conscious RTWO with reliable direction control of the wave propagation was investigated. The phase noise was analyzed based on the proposed RTWO. The phase noise reduction technique was introduced by using tail current source filtering technique in which a figure-8 inductors were employed. Three RTWO were implemented based on GF 130 nm standard CMOS process and TSMC 130 nm standard CMOS process. The first design was achieving 16-GHz frequency with power consumption of 5.8-mW with 190.3 dBc/Hz FoM at 1 MHz offset. The second and third design were operating at 14-GHz with a power consumption range of 13-18.4mW and 14.6-20.5mW, respectively. The one with filtering technique achieved FoM of 184.8 dBc/Hz at 1 MHz whereas the one without inudctor filtering obtained FoM of 180.8 dBc/Hz at 1 MHz offset based on simulation

Modeling and simulation of VLSI interconnections with moments

Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1989.Includes bibliographical references.Supported in part by the Joint Services Electronics Program. DAAL03-86-K-0002Steven Paul McCormick