112 research outputs found

    Advanced analog layout design automation in compliance with density uniformity

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    To fabricate a reliable integrated circuit chip, foundries follow specific design rules and layout processing techniques. One of the parameters, which affect circuit performance and final electronic product quality, is the variation of thickness for each semiconductor layer within the fabricated chips. The thickness is closely dependent on the density of geometric features on that layer. Therefore, to ensure consistent thickness, foundries normally have to seriously control distribution of the feature density on each layer by using post-processing operations. In this research, the methods of controlling feature density distribution on different layers of an analog layout during the process of layout migration from an old technology to a new one or updated design specifications in the same technology have been investigated. We aim to achieve density-uniformity-aware layout retargeting for facilitating manufacturing process in the advanced technologies. This can offer an advantage right to the design stage for the designers to evaluate the effects of applying density uniformity to their drafted layouts, which are otherwise usually done by the foundries at the final manufacturing stage without considering circuit performance. Layout modification for density uniformity includes component position change and size modification, which may induce crosstalk noise caused by extra parasitic capacitance. To effectively control this effect, we have also investigated and proposed a simple yet accurate analytic method to model the parasitic capacitance on multi-layer VLSI chips. Supported by this capacitance modeling research, a unique methodology to deal with density-uniformity-aware analog layout retargeting with the capability of parasitic capacitance control has been presented. The proposed operations include layout geometry position rearrangement, interconnect size modification, and extra dummy fill insertion for enhancing layout density uniformity. All of these operations are holistically coordinated by a linear programming optimization scheme. The experimental results demonstrate the efficacy of the proposed methodology compared to the popular digital solutions in terms of minimum density variation and acute parasitic capacitance control

    Critical area driven dummy fill insertion to improve manufacturing yield

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    Robust signaling techniques for through silicon via bundles

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    34th Midwest Symposium on Circuits and Systems-Final Program

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    Organized by the Naval Postgraduate School Monterey California. Cosponsored by the IEEE Circuits and Systems Society. Symposium Organizing Committee: General Chairman-Sherif Michael, Technical Program-Roberto Cristi, Publications-Michael Soderstrand, Special Sessions- Charles W. Therrien, Publicity: Jeffrey Burl, Finance: Ralph Hippenstiel, and Local Arrangements: Barbara Cristi

    Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

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    This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results

    BULK-PIEZOELECTRIC TRANSDUCTION OF MICROSYSTEMS WITH APPLICATIONS TO BATCH-ASSEMBLY OF MICROMIRRORS, CAPACITIVE SENSING, AND SOLAR ENERGY CONCENTRATION

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    Electromechanical modeling, actuation, sensing and fabrication aspects of bulkpiezoelectric ceramic integration for microsystems are investigated in this thesis. A small-signal model that describes the energy exchange between surface micromachined beams and bulk-lead zirconium titanate (PZT) actuators attached to the silicon substrate is presented. The model includes detection of acoustic waves launched from electrostatically actuated structures on the surface of the die, as well as their actuation by bulk waves generated by piezoelectric ceramics. The interaction is modeled via an empirical equivalent circuit, which is substantiated by experiments designed to extract the model parameters. As a die level application of bulk-PZT, an Ultrasound Enhanced Electrostatic Batch Assembly (U2EBA) method for realization of 3-D microsystems is demonstrated. U2EBA involves placing the die in an external DC electric field perpendicular to the substrate and actuating the die with an off-chip, bulk-piezoelectric ceramic. Yield rates reaching up to 100% are reported from 8×8 arrays of hinged mirrors with dimensions of 180 × 100 micrometre-squared. U2EBA is later improved to provide temporary latching at intermediate angles between fully horizontal and vertical states, by using novel latching structures. It is shown that the micromirrors can be trapped and freed from different rotation angles such that zero static power is needed to maintain an angular position. The zero-idle-power positioning of large arrays of small mirrors is later investigated for energy redirection and focusing. All-angle LAtchable Reflector (ALAR) concept is introduced, and its application to Concentrated Solar Power (CSP) systems is discussed. The main premise of ALAR technology is to replace bulky and large arrays of mirrors conventionally used in CSP technologies with zeroidle- power, semi-permanently latched, low-profile, high-fill factor, micrometer to centimeter scale mirror arrays. A wirelessly controlled prototype that can move a 2-D array of mirrors, each having a side length of less than 5 cm, in two degrees of freedom to track the brightest spot in the ambient is demonstrated. Capacitive sensing using bulk-piezoelectric crystals is investigated, and a Time- Multiplexed Crystal based Capacitive Sensing (TM-XCS) method is proposed to provide nonlinearity compensation and self-temperature sensing for oscillator based capacitive sensors. The analytical derivation of the algorithm and experimental evidence regarding the validity of some of the relations used in the derivation are presented. This thesis also presents results on microfluidic particle transport as another application of bulk-PZT in microsystems. Experiments and work regarding actuation of micro-scale, fluorescent beads on silicon nitride membranes are described

    VLSI Design

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    This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

    Uniquely Identifiable Tamper-Evident Device Using Coupling between Subwavelength Gratings

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    Reliability and sensitive information protection are critical aspects of integrated circuits. A novel technique using near-field evanescent wave coupling from two subwavelength gratings (SWGs), with the input laser source delivered through an optical fiber is presented for tamper evidence of electronic components. The first grating of the pair of coupled subwavelength gratings (CSWGs) was milled directly on the output facet of the silica fiber using focused ion beam (FIB) etching. The second grating was patterned using e-beam lithography and etched into a glass substrate using reactive ion etching (RIE). The slightest intrusion attempt would separate the CSWGs and eliminate near-field coupling between the gratings. Tampering, therefore, would become evident. Computer simulations guided the design for optimal operation of the security solution. The physical dimensions of the SWGs, i.e. period and thickness, were optimized, for a 650 nm illuminating wavelength. The optimal dimensions resulted in a 560 nm grating period for the first grating etched in the silica optical fiber and 420 nm for the second grating etched in borosilicate glass. The incident light beam had a half-width at half-maximum (HWHM) of at least 7 µm to allow discernible higher transmission orders, and a HWHM of 28 µm for minimum noise. The minimum number of individual grating lines present on the optical fiber facet was identified as 15 lines. Grating rotation due to the cylindrical geometry of the fiber resulted in a rotation of the far-field pattern, corresponding to the rotation angle of moiré fringes. With the goal of later adding authentication to tamper evidence, the concept of CSWGs signature was also modeled by introducing random and planned variations in the glass grating. The fiber was placed on a stage supported by a nanomanipulator, which permitted three-dimensional displacement while maintaining the fiber tip normal to the surface of the glass substrate. A 650 nm diode laser was fixed to a translation mount that transmitted the light source through the optical fiber, and the output intensity was measured using a silicon photodiode. The evanescent wave coupling output results for the CSWGs were measured and compared to the simulation results
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