24 research outputs found
Design and Analysis of Power Distribution Networks in VLSI Circuits.
Rapidly switching currents of the on-chip devices can cause fluctuations in the supply voltage which can be classified as IR and Ldi/dt drops. The voltage fluctuations in a supply network can inject noise in a circuit which may lead to functional failures of the design. Power supply integrity verification is, therefore, a critical concern in high-performance designs. Also, with decreasing supply voltages, gate-delay is becoming increasingly sensitive to supply voltage variation. With ever-diminishing clock periods, accurate analysis of the impact of supply voltage on circuit performance has also become critical.
Increasing power consumption and clock frequency have exacerbated the Ldi/dt drop in every new technology generation. The Ldi/dt drop has become the dominant portion of the overall supply-drop in high performance designs. On-die passive decap, which has traditionally been used for suppressing Ldi/dt, has become expensive due to its area and leakage power overhead. This has created an urgent need for novel circuit techniques to suppress the Ldi/dt drop in power distribution networks.
We provide accurate algorithmic solutions for determining the worst-case supply-drop and the impact of supply noise on circuit performance. We propose a path-based and a block-based approach for computing the maximum circuit delay under power supply fluctuations. We also propose an early-mode supply-drop estimation approach and a statistical approach for power grid analysis. All the proposed approaches are vectorless and account for both IR and Ldi/dt drops. We also propose a performance-aware decoupling capacitance allocation technique which uses timing slacks to drive the optimization.
Finally, we present analog as well as all-digital circuit techniques for inductive supply noise suppression. The proposed all-digital circuit techniques were implemented in a test-chip, fabricated in a 0.13µm CMOS process. Measurements on the test-chip demonstrate a reduction in the supply fluctuations by 57% for a ramp loads and by 75% during resonance. We also present a low-power, all-digital on-chip oscilloscope for accurate measurement of supply noise. Supply noise measurements obtained from the on-chip oscilloscope were validated to conform well to those obtained from a traditional supply-drop monitor and direct on-chip probing.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/58508/1/spant_1.pd
Secure Physical Design
An integrated circuit is subject to a number of attacks including information leakage, side-channel attacks, fault-injection, malicious change, reverse engineering, and piracy. Majority of these attacks take advantage of physical placement and routing of cells and interconnects. Several measures have already been proposed to deal with security issues of the high level functional design and logic synthesis. However, to ensure end-to-end trustworthy IC design flow, it is necessary to have security sign-off during physical design flow. This paper presents a secure physical design roadmap to enable end-to-end trustworthy IC design flow. The paper also discusses utilization of AI/ML to establish security at the layout level. Major research challenges in obtaining a secure physical design are also discussed
Multiphysics modeling and simulation for large-scale integrated circuits
This dissertation is a process of seeking solutions to two important and challenging problems related to the design of modern integrated circuits (ICs): the ever increasing couplings among the multiphysics and the large problem size arising from the escalating complexity of the designs. A multiphysics-based computer-aided design methodology is proposed and realized to address multiple aspects of a design simultaneously, which include electromagnetics, heat transfer, fluid dynamics, and structure mechanics. The multiphysics simulation is based on the finite element method for its unmatched capabilities in handling complicate geometries and material properties. The capability of the multiphysics simulation is demonstrated through its applications in a variety of important problems, including the static and dynamic IR-drop analyses of power distribution networks, the thermal-ware high-frequency characterization of through-silicon-via structures, the full-wave electromagnetic analysis of high-power RF/microwave circuits, the modeling and analysis of three-dimensional ICs with integrated microchannel cooling, the characterization of micro- and nanoscale electrical-mechanical systems, and the modeling of decoupling capacitor derating in the power integrity simulations. To perform the large-scale analysis in a highly efficient manner, a domain decomposition scheme, parallel computing, and an adaptive time-stepping scheme are incorporated into the proposed multiphysics simulation. Significant reduction in computation time is achieved through the two numerical schemes and the parallel computing with multiple processors
Asynchronous circuit simulation and design methodologies
The purpose of this thesis is to examine asynchronous design as a possible alternative to synchronous design. Asynchronous design promises better power consumption and higher performance. In this thesis an asynchronous simulator capable of predicting asynchronous system performance is designed. The simulator is based on a probabilistic event driven model of asynchronous elements. The simulator is performance oriented only, and thus is not capable of functional simulation or verification. It provides a highly abstract view of the system. Using the simulator several design methodologies were inspected and simulated for their performance. Particular attention is paid to differences between synchronous and asynchronous methodologies. In addition several current sensor techniques were examined as a possible way of implementing asynchronous circuit completion detection. The contribution of this thesis is definition of the reasons why the current sensing is not a feasible way for completion detection, and the ability to predict the asynchronous system behavior on an architectural level
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High-Speed Wide-Field Time-Correlated Single-Photon Counting Fluorescence Lifetime Imaging Microscopy
Fluorescence microscopy is a powerful imaging technique used in the biological sciences to identify labeled components of a sample with specificity. This is usually accomplished through labeling with fluorescent dyes, isolating these dyes by their spectral signatures with optical filters, and recording the intensity of the fluorescent response. Although these techniques are widely used, fluorescence intensity images can be negatively affected by a variety of factors that impact the fluorescence intensity. Fluorescence lifetime imaging microscopy (FLIM) is an imaging technique that is relatively immune to intensity fluctuations and also provides the unique ability to directly monitor the microenvironment surrounding a fluorophore. Despite the benefits associated with FLIM, the applications to which it is applied are fairly limited due to long image acquisition times and high cost of traditional hardware. Recent advances in complementary metal-oxide-semiconductor (CMOS) single-photon avalanche diodes (SPADs) have enabled the design of low-cost imaging arrays that are capable of recording lifetime images with acquisition times greater than one order of magnitude faster than existing systems. However, these SPAD arrays have yet to realize the full potential of the technology due to limitations in their ability to handle the vast amount of data generated during the commonly used time-correlated single-photon counting (TCSPC) lifetime imaging technique. This thesis presents the design, implementation, characterization, and demonstration of a high speed FLIM imaging system. The components of this design include a CMOS imager chip in a standard 0.13 μm technology containing a custom CMOS SPAD, a 64-by-64 array of these SPADs, pixel control circuitry, independent time-to-digital converters (TDCs), a FLIM specific datapath, and high bandwidth output buffers. In addition to the CMOS imaging array, a complete system was designed and implemented using a printed circuit board (PCB) for capturing data from the imager, creating histograms for the photon arrival data using field-programmable gate arrays, and transferring the data to a computer using a cabled PCIe interface. Finally, software is used to communicate between the imaging system and a computer.The dark count rate of the SPAD was measured to be only 231 Hz at room temperature while maintaining a photon detection probability of up to 30\%. TDCs included on the array have a 62.5 ps resolution and a 64 ns range, which is suitable for measuring the lifetime of most biological fluorophores. Additionally, the on-chip datapath was designed to handle continuous data transfers at rates capable of supporting TCSPC-based lifetime imaging at 100 frames per second. The system level implementation also provides sufficient data throughput for transferring up to 750 frames per second from the imaging system to a computer. The lifetime imaging system was characterized using standard techniques for evaluating SPAD performance and an electrical delay signal for measuring the TDC performance. This thesis concludes with a demonstration of TCSPC-FLIM imaging at 100 frames per second -- the fastest 64-by-64 TCSPC FLIM that has been demonstrated. This system overcomes some of the limitations of existing FLIM systems and has the potential to enable new application domains in dynamic FLIM imaging
Memory Hierarchy Design for Next Generation Scalable Many-core Platforms
Performance and energy consumption in modern computing platforms is largely dominated by the memory hierarchy. The increasing computational power in the multiprocessors and accelerators, and the emergence of the data-intensive workloads (e.g. large-scale graph traversal and scientific algorithms) requiring fast transfer of large volumes of data, are two main trends which intensify this problem by putting even higher pressure on the memory hierarchy. This increasing gap between computation speed and data transfer speed is commonly referred as the “memory wall” problem. With the emergence of heterogeneous Three Dimensional (3D) Integration based on through-silicon-vias (TSV), this situation has started to recover in the past years. On one hand, it is now possible to improve memory access bandwidth and/or latency by either stacking memories directly on top of processors or through abstracted memory interfaces such as Micron’s Hybrid Memory Cube (HMC). On the other hand, near memory computation has become worthy of revisiting due to the cost-effective integration of logic and memory in 3D stacks. These two directions bring about several interesting opportunities including performance improvement, energy and cost reduction, product miniaturization, and modular design for improved time to market. In this research, we study the effectiveness of the 3D integration technology and the optimization opportunities which it can provide in the different layers of the memory hierarchy in cluster-based many-core platforms ranging from intra-cluster L1 to inter-cluster L2 scratchpad memories (SPMs), as well as the main memory. In addition, by moving a part of the computation to where data resides, in the 3D-stacked memory context, we demonstrate further energy and performance improvement opportunities
Muon (g-2) Technical Design Report
The Muon (g-2) Experiment, E989 at Fermilab, will measure the muon anomalous magnetic moment a factor-of-four more precisely than was done in E821 at the Brookhaven National Laboratory AGS. The E821 result appears to be greater than the Standard-Model prediction by more than three standard deviations. When combined with expected improvement in the Standard-Model hadronic contributions, E989 should be able to determine definitively whether or not the E821 result is evidence for physics beyond the Standard Model. After a review of the physics motivation and the basic technique, which will use the muon storage ring built at BNL and now relocated to Fermilab, the design of the new
experiment is presented. This document was created in partial fulfillment of the requirements necessary to obtain DOE CD-2/3 approval
Thermal-Hydraulics in Nuclear Fusion Technology: R&D and Applications
In nuclear fusion technology, thermal-hydraulics is a key discipline employed in the design phase of the systems and components to demonstrate performance, and to ensure the reliability and their efficient and economical operation. ITER is in charge of investigating the transients of the engineering systems; this included safety analysis. The thermal-hydraulics is required for the design and analysis of the cooling and ancillary systems such as the blanket, the divertor, the cryogenic, and the balance of plant systems, as well as the tritium carrier, extraction and recovery systems. This Special Issue collects and documents the recent scientific advancements which include, but are not limited to: thermal-hydraulic analyses of systems and components, including magneto-hydrodynamics; safety investigations of systems and components; numerical models and code development and application; codes coupling methodology; code assessment and validation, including benchmarks; experimental infrastructures design and operation; experimental campaigns and investigations; scaling issue in experiments