A low-speed BIST framework for high-performance circuit testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addresse

Fuse: A technique to anticipate failures due to degradation in ALUs

This paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (arithmetic logic unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder and the circuitry required to measure its degradation. By mimicking the behavior of the replicated transistor the fuse anticipates the failure short before the first failure in the adder appears, and hence, data corruption and program crashes can be avoided. Our results show that the fuse anticipates the failure in more than 99.9% of the cases after 96.6% of the lifetime, even for pessimistic random within-die variations.Peer ReviewedPostprint (published version

Combined Time and Information Redundancy for SEU-Tolerance in Energy-Efficient Real-Time Systems

Recently the trade-off between energy consumption and fault-tolerance in real-time systems has been highlighted. These works have focused on dynamic voltage scaling (DVS) to reduce dynamic energy dissipation and on time redundancy to achieve transient-fault tolerance. While the time redundancy technique exploits the available slack time to increase the fault-tolerance by performing recovery executions, DVS exploits slack time to save energy. Therefore we believe there is a resource conflict between the time-redundancy technique and DVS. The first aim of this paper is to propose the usage of information redundancy to solve this problem. We demonstrate through analytical and experimental studies that it is possible to achieve both higher transient fault-tolerance (tolerance to single event upsets (SEU)) and less energy using a combination of information and time redundancy when compared with using time redundancy alone. The second aim of this paper is to analyze the interplay of transient-fault tolerance (SEU-tolerance) and adaptive body biasing (ABB) used to reduce static leakage energy, which has not been addressed in previous studies. We show that the same technique (i.e. the combination of time and information redundancy) is applicable to ABB-enabled systems and provides more advantages than time redundancy alone

An Approach to Assess Solder Interconnect Degradation Using Digital Signal

Department of Human and Systems EngineeringDigital signals used in electronic systems require reliable data communication. It is necessary to monitor the system health continuously to prevent system failure in advance. Solder joints in electronic assemblies are one of the major failure sites under thermal, mechanical and chemical stress conditions during their operation. Solder joint degradation usually starts from the surface where high speed signals are concentrated due to the phenomenon referred to as the skin effect. Due to the skin effect, high speed signals are sensitive when detecting the early stages of solder joint degradation. The objective of the thesis is to assess solder joint degradation in a non-destructive way based on digital signal characterization. For accelerated life testing the stress conditions were designed in order to generate gradual degradation of solder joints. The signal generated by a digital signal transceiver was travelling through the solder joints to continuously monitor the signal integrity under the stress conditions. The signal properities were obtained by eye parameters and jitter, which represented the characteristics of the digital signal in terms of noise and timing error. The eye parameters and jitter exhibited significant increase after the exposure of the solder joints to the stress conditions. The test results indicated the deterioration of the signal integrity resulted from the solder joint degradation, and proved that high speed digital signals could serve as a non-destructive tool for sensing physical degradation. Since this approach is based on the digital signals used in electronic systems, it can be implemented without requiring additional sensing devices. Furthermore, this approach can serve as a proactive prognostic tool, which provides real-time health monitoring of electronic systems and triggers early warning for impending failure.ope

Development of reliability methodology for systems engineering. Volume II - Application - Design reliability analysis of a 250 volt-ampere static inverter Final report

Design stage reliability analysis application to static inverte

Pcm telemtry- a new approach using all- magnetic techniques

Digital all-magnetic circuit technique used in pulse code modulation telemetry system