Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

Asynchronous techniques for system-on-chip design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed

On the design of an energy-efficient low-latency integrated protocol for distributed mobile sensor networks

Self organizing, wireless sensors networks are an emergent and challenging technology that is attracting large attention in the sensing and monitoring community. Impressive progress has been done in recent years even if we need to assume that an optimal protocol for every kind of sensor network applications can not exist. As a result it is necessary to optimize the protocol for certain scenarios. In many applications for instance latency is a crucial factor in addition to energy consumption. MERLIN performs its best in such WSNs where there is the need to reduce the latency while ensuring that energy consumption is kept to a minimum. By means of that, the low latency characteristic of MERLIN can be used as a trade off to extend node lifetimes. The performance in terms of energy consumption and latency is optimized by acting on the slot length. MERLIN is designed specifically to integrate routing, MAC and localization protocols together. Furthermore it can support data queries which is a typical application for WSNs. The MERLIN protocol eliminates the necessity to have any explicit handshake mechanism among nodes. Furthermore, the reliability is improved using multiple path message propagation in combination with an overhearing mechanism. The protocol divides the network into subsets where nodes are grouped in time zones. As a result MERLIN also shows a good scalability by utilizing an appropriate scheduling mechanism in combination with a contention period

DPA on quasi delay insensitive asynchronous circuits: formalization and improvement

The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a formal modeling of the electrical signature of QDI asynchronous circuits. The DPA is then applied to the formal model in order to identify the source of leakage of this type of circuits. Finally, a complete design flow is specified to minimize the information leakage. The relevancy and efficiency of the approach is demonstrated using the design of an AES crypto-processor.Comment: Submitted on behalf of EDAA (http://www.edaa.com/

Asynchronous Circuits as an Enabler of Scalable And Programmable Metasurfaces

Metamaterials and metasurfaces have given possibilities for manipulating electromagnetic (EM) waves that in the past would have seemed impossible. The majority of metasurface designs are suitable for a particular frequency and angle of incidence. One long-sought objective is the design of programmable metasurfaces to dynamically manipulate a variety of incoming EM frequencies and angles. In order to do this, a large-scale mesh of networked chips are required below the metasurface, which apart from adapting electrical impedance properties, also communicate with each other, thus relaying information about meta-atom settings, as well as forwarding possible distributed measurements taken. This paper describes why an asynchronous mixed-signal ASIC is advantageous for the control of scalable, EM absorbing, metasurfaces

Design of Asynchronous Processor

There has been a resurgence of interest in asynchronous design recently. The renewed interest in asynchronous design results from its potential to address the problem faced by the synchronous design methodology. In asynchronous methodology, there is no global clock controlling the synchronization of a circuit; instead, the data communication between each functional unit is completed through local request-acknowledge handshake protocol. The growth in demand of high performance portable systems has accelerated asynchronous logic design technique which can offers better performance and lower power consumption especially in the development of the asynchronous processor for mobile and portable application. In this thesis, the design and verification of an 8-bit asynchronous pipelined processor is presented. The developed asynchronous processor is based on Harvard architecture and uses Reduced Instruction Set Computer (RISC) instruction set architecture. 24 instructions are supported by the processor including register, memory, branch and jump operations. The processor has three-stage pipelining i.e. fetch, decode and execution pipeline. Micropipelines framework with 2-phase signalling protocol and bundled-data approach is employed in designing complex and powerful asynchronous control circuits for the processor. Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to design and construct all parts of the asynchronous processor. Simulation, synthesis and verification of the processor are carried out using MAX +PLUS II software. The simulation results have demonstrated that the developed 8-bit asynchronous RISC processor is working correctly using current Field Programmable Gate Array (FPGA) technology. This processor employed 903 logic cells and has 6144 memory bits for instruction and data memory. Each of the processor subsystem can operates at different cycle time, thus enable an asynchronous processor achieving 11.95MHz average speed performance