Comparison of matroid intersection algorithms for large circuit analysis

This paper presents two approaches to symbolic analysis of large analog integrated circuits via simplification during the generation of the symbolic expressions. Both techniques are examined from the point of view of matroid theory. Finally, a new approach which combines the positive features of both approaches is introduced

FFTPL: An Analytic Placement Algorithm Using Fast Fourier Transform for Density Equalization

We propose a flat nonlinear placement algorithm FFTPL using fast Fourier transform for density equalization. The placement instance is modeled as an electrostatic system with the analogy of density cost to the potential energy. A well-defined Poisson's equation is proposed for gradient and cost computation. Our placer outperforms state-of-the-art placers with better solution quality and efficiency

Secret-free security: a survey and tutorial

Classical keys, i.e., secret keys stored permanently in digital form in nonvolatile memory, appear indispensable in modern computer security-but also constitute an obvious attack target in any hardware containing them. This contradiction has led to perpetual battle between key extractors and key protectors over the decades. It is long known that physical unclonable functions (PUFs) can at least partially overcome this issue, since they enable secure hardware without the above classical keys. Unfortunately, recent research revealed that many standard PUFs still contain other types of secrets deeper in their physical structure, whose disclosure to adversaries breaks security as well: Examples include the manufacturing variations in SRAM PUFs, the power-up states of SRAM PUFs, or the signal delays in Arbiter PUFs. Most of these secrets have already been extracted in viable attacks in the past, breaking PUF-security in practice. A second generation of physical security primitives now shows potential to resolve this remaining problem, however. In certain applications, so-called Complex PUFs, SIMPLs/PPUFs, and UNOs are able to realize not just hardware that is free of classical keys in the above sense, but completely secret-free instead. In the resulting hardware systems, adversaries could hypothetically be allowed to inspect every bit and every atom, and learn any information present in any form in the system, without being able to break security. Secret-free hardware would hence promise to be innately and permanently immune against any physical or malware-based key-extraction: There simply is no security-critical information to extract anymore. Our survey and tutorial paper takes the described situation as starting point, and categorizes, formalizes, and overviews the recently evolving area of secret-free security. We propose the attempt of making hardware completely secret-free as promising endeavor in future hardware designs, at least in those application scenarios where this is logically possible. In others, we suggest that secret-free techniques could be combined with standard PUFs and classical methods to construct hybrid systems with notably reduced attack surfaces

Journal of Shock and Hemodynamics, Vol 1., Iss. 1 (Print Version)

The print version of Volume I, Issue I of the Journal of Shock and Hemodynamics was published in September 2022. The PDF of the print version is downloadable here

An update of commercial infrared sensing and imaging instruments

A classification of infrared sensing instruments by type and application, listing commercially available instruments, from single point thermal probes to on-line control sensors, to high speed, high resolution imaging systems is given. A review of performance specifications follows, along with a discussion of typical thermographic display approaches utilized by various imager manufacturers. An update report on new instruments, new display techniques and newly introduced features of existing instruments is given

3D IC optimal layout design. A parallel and distributed topological approach

The task of 3D ICs layout design involves the assembly of millions of components taking into account many different requirements and constraints such as topological, wiring or manufacturability ones. It is a NP-hard problem that requires new non-deterministic and heuristic algorithms. Considering the time complexity, the commonly applied Fiduccia-Mattheyses partitioning algorithm is superior to any other local search method. Nevertheless, it can often miss to reach a quasi-optimal solution in 3D spaces. The presented approach uses an original 3D layout graph partitioning heuristics implemented with use of the extremal optimization method. The goal is to minimize the total wire-length in the chip. In order to improve the time complexity a parallel and distributed Java implementation is applied. Inside one Java Virtual Machine separate optimization algorithms are executed by independent threads. The work may also be shared among different machines by means of The Java Remote Method Invocation system.Comment: 26 pages, 9 figure

DC Admittance Model of VSCs for Stability Studies in VSC-HVDC Systems

High-voltage direct current (HVDC) systems linked to AC grids with converters are promising energy transmission systems. These systems present complex AC- and DC-side dynamic interactions. Impedance-based stability studies have recently been proposed to assess DC-side dynamics from DC-side characterization of voltage source converters (VSCs) considering AC-side dynamics. However, the existing approaches used for stability studies in VSC-HVDC systems do not completely model VSCs because they do not consider together the VSC delay, the grid voltage feedforward filter, and all the d- and q-reference current controls. Moreover, these approaches are analytically characterized from dq-real space vectors (less related to circuit theory than dq-complex space vectors), and some work with simple AC grids. The main contribution of this paper is a detailed and complete DC admittance model of VSCs from dq-complex space vectors, which considers the VSC delay, feedforward filter, and d- and q-reference current controls, and also a general AC grid. The proposed model can be used for DC-side stability studies in VSC-HVDC systems considering AC grid dynamics. The capabilities and drawbacks of impedance-based stability methods for DC-side stability assessment were analyzed, and the positive-net-damping criterion was validated as a robust approach. The model was validated by PSCAD/EMTDC simulations and applied to a stability study in a VSC-HVDC system.info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2021-2023/PID2021-123633OB-C33/ES/Estabilidad de microrredes formadas por agrupaciones de clustersObjectius de Desenvolupament Sostenible::7 - Energia Assequible i No ContaminantObjectius de Desenvolupament Sostenible::7 - Energia Assequible i No Contaminant::7.2 - Per a 2030, augmentar substancialment el percentatge d’energia renovable en el con­junt de fonts d’energiaObjectius de Desenvolupament Sostenible::7 - Energia Assequible i No Contaminant::7.b - Per a 2030, ampliar la infraestructura i millorar la tecnologia per tal d’oferir serveis d’energia moderns i sos­tenibles per a tots els països en desenvolupament, en particular els països menys avançats, els petits estats insulars en desenvolupament i els països en desenvolupament sense litoral, d’acord amb els programes de suport respectiusObjectius de Desenvolupament Sostenible::9 - Indústria, Innovació i InfraestructuraObjectius de Desenvolupament Sostenible::9 - Indústria, Innovació i Infraestructura::9.4 - Per a 2030, modernitzar les infraestructures i reconvertir les indústries perquè siguin sostenibles, usant els recursos amb més eficàcia i promovent l’adopció de tecnologies i processos industrials nets i racionals ambiental­ment, i aconseguint que tots els països adoptin mesures d’acord amb les capacitats respectivesPostprint (published version