Fbb Cmos Tapered Buffer With Optimal Vth Selection

This paper represents fixed body biased CMOS Tapered Buffer which is designed to minimize the PDP (Power Delay Product) of the circuit. CMOS Tapered Buffers are often used for driving large capacitive load at high speed. Since there are tradeoffs between performance parameters of Buffer for minimizing its PDP value and due to technology constraints on the threshold voltage of MOS; one can vary the Vth up to certain limit while keeping the VDD constant. The proposed work is helpful in designing power efficient CMOS Tapered Buffer. This is found that in proposed Buffer when Vth value for the first stage of inverter is taken between the range of (0.2VDD - 0.4 VDD), its performance gets improved in terms of power dissipation. This analysis is verified by simulating the 2-stage Tapered buffer using standard 180nm CMOS technology in Cadence environment. Analysis performed on the schematic shows that FBB (Fixed Body Bias) Tapered Buffer reduces the average power dissipation across capacitive load by 77% and static power has been reduced to 18.3% at very less penalty in delay. Hence the proposed approach is suitable in the design of low power buffer for increasing the current capability of logic gate at optimal speed

An Ultra-Low-Power Track-and-Hold Amplifier

The future of electronics is the Internet of Things (IoT) paradigm, where always-on devices and sensors monitor and transform everyday life. A plethora of applications (such as navigating drivers past road hazards or monitoring bridge and building stresses) employ this technology. These unattended ground-sensor applications require decade(s)-long operational life-times without battery changes. Such electronics demand stringent performance specifications with only nano-Watt power levels.This thesis presents an ultra-low-power track-and-hold amplifier for such systems. It serves as the front-end of a SAR-ADC or the building block for equalizers or filters. This amplifier\u27s design attains exceptional hold times by mitigating switch subthreshold leakage and bulk leakage. Its novel transmission-gate topology achieves wide-swing performance. Though only consuming 100 pico-Watts, it achieves a precision of 7.6 effective number of bits (ENOB). The track-and-hold amplifier was designed in 130-nm CMOS

Investigation of charge coupled device correlation techniques

Analog Charge Transfer Devices (CTD's) offer unique advantages to signal processing systems, which often have large development costs, making it desirable to define those devices which can be developed for general system's use. Such devices are best identified and developed early to give system's designers some interchangeable subsystem blocks, not requiring additional individual development for each new signal processing system. The objective of this work is to describe a discrete analog signal processing device with a reasonably broad system use and to implement its design, fabrication, and testing

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

Power reduction techniques for memory elements

High performance and computational capability in the current generation processors are made possible by small feature sizes and high device density. To maintain the current drive strength and control the dynamic power in these processors, simultaneous scaling down of supply and threshold voltages is performed. High device density and low threshold voltages result in an increase in the leakage current dissipation. Large on chip caches are integrated onto the current generation processors which are becoming a major contributor to total leakage power. In this work, a novel methodology is proposed to minimize the leakage power and dynamic power. The proposed static power reduction technique, GALEOR (GAted LEakage transistOR), introduces stacks by placing high threshold voltage transistors and consists of inherent control logic. The proposed dynamic power reduction technique, adaptive phase tag cache, achieves power savings through varying tag size for a design window. Testing and verification of the proposed techniques is performed on a two level cache system. Power delay squared product is used as a metric to measure the effectiveness of the proposed techniques. The GALEOR technique achieves 30% reduction when implemented on CMOS benchmark circuits and an overall leakage savings of 9% when implemented on the two level cache systems. The proposed dynamic power reduction technique achieves 10% savings when implemented on individual modules of the two level cache and an overall savings of 3% when implemented on the entire two level cache system

Low-power CMOS front-ends for wireless personal area networks

The potential of implementing subthreshold radio frequency circuits in deep sub-micron CMOS technology was investigated for developing low-power front-ends for wireless personal area network (WPAN) applications. It was found that the higher transconductance to bias current ratio in weak inversion could be exploited in developing low-power wireless front-ends, if circuit techniques are employed to mitigate the higher device noise in subthreshold region. The first fully integrated subthreshold low noise amplifier was demonstrated in the GHz frequency range requiring only 260 μW of power consumption. Novel subthreshold variable gain stages and down-conversion mixers were developed. A 2.4 GHz receiver, consuming 540 μW of power, was implemented using a new subthreshold mixer by replacing the conventional active low noise amplifier by a series-resonant passive network that provides both input matching and voltage amplification. The first fully monolithic subthreshold CMOS receiver was also implemented with integrated subthreshold quadrature LO (Local Oscillator) chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage amplification, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling were combined to lower the total power consumption to 2.6 mW. Extremely compact resistive feedback CMOS low noise amplifiers were presented as a cost-effective alternative to narrow band LNAs using high-Q inductors. Techniques to improve linearity and reduce power consumption were presented. The combination of high linearity, low noise figure, high broadband gain, extremely small die area and low power consumption made the proposed LNA architecture a compelling choice for many wireless applications.Ph.D.Committee Chair: Laskar, Joy; Committee Member: Chakraborty, Sudipto; Committee Member: Chang, Jae Joon; Committee Member: Divan, Deepakraj; Committee Member: Kornegay, Kevin; Committee Member: Tentzeris, Emmanoui