81 research outputs found
Analog Spiking Neuromorphic Circuits and Systems for Brain- and Nanotechnology-Inspired Cognitive Computing
Human society is now facing grand challenges to satisfy the growing demand for computing power, at the same time, sustain energy consumption. By the end of CMOS technology scaling, innovations are required to tackle the challenges in a radically different way. Inspired by the emerging understanding of the computing occurring in a brain and nanotechnology-enabled biological plausible synaptic plasticity, neuromorphic computing architectures are being investigated. Such a neuromorphic chip that combines CMOS analog spiking neurons and nanoscale resistive random-access memory (RRAM) using as electronics synapses can provide massive neural network parallelism, high density and online learning capability, and hence, paves the path towards a promising solution to future energy-efficient real-time computing systems. However, existing silicon neuron approaches are designed to faithfully reproduce biological neuron dynamics, and hence they are incompatible with the RRAM synapses, or require extensive peripheral circuitry to modulate a synapse, and are thus deficient in learning capability. As a result, they eliminate most of the density advantages gained by the adoption of nanoscale devices, and fail to realize a functional computing system.
This dissertation describes novel hardware architectures and neuron circuit designs that synergistically assemble the fundamental and significant elements for brain-inspired computing. Versatile CMOS spiking neurons that combine integrate-and-fire, passive dense RRAM synapses drive capability, dynamic biasing for adaptive power consumption, in situ spike-timing dependent plasticity (STDP) and competitive learning in compact integrated circuit modules are presented. Real-world pattern learning and recognition tasks using the proposed architecture were demonstrated with circuit-level simulations. A test chip was implemented and fabricated to verify the proposed CMOS neuron and hardware architecture, and the subsequent chip measurement results successfully proved the idea.
The work described in this dissertation realizes a key building block for large-scale integration of spiking neural network hardware, and then, serves as a step-stone for the building of next-generation energy-efficient brain-inspired cognitive computing systems
Mathematical simulation of memristive for classification in machine learning
Over the last few years, neuromorphic computation has been a widely researched topic. One of the neuromorphic computation elements is the memristor. The memristor is a high density, analogue memory storage, and compliance with Ohm's law for minor potential changes. Memristive behaviour imitates synaptic behaviour. It is a nanotechnology that can reduce power consumption, improve synaptic modeling, and reduce data transmission processes. The purpose of this paper is to investigate a customized mathematical model for machine learning algorithms. This model uses a computing paradigm that differs from standard Von-Neumann architectures, and it has the potential to reduce power consumption and increasing performance while doing specialized jobs when compared to regular computers. Classification is one of the most interesting fields in machine learning to classify features patterns by using a specific algorithm. In this study, a classifier based memristive is used with an adaptive spike encoder for input data. We run this algorithm based on Anti-Hebbian and Hebbian learning rules. These investigations employed two of datasets, including breast cancer Wisconsin and Gaussian mixture model datasets. The results indicate that the performance of our algorithm that has been used based on memristive is reasonably close to the optimal solution
Neuro-memristive Circuits for Edge Computing: A review
The volume, veracity, variability, and velocity of data produced from the
ever-increasing network of sensors connected to Internet pose challenges for
power management, scalability, and sustainability of cloud computing
infrastructure. Increasing the data processing capability of edge computing
devices at lower power requirements can reduce several overheads for cloud
computing solutions. This paper provides the review of neuromorphic
CMOS-memristive architectures that can be integrated into edge computing
devices. We discuss why the neuromorphic architectures are useful for edge
devices and show the advantages, drawbacks and open problems in the field of
neuro-memristive circuits for edge computing
Neuromorphic Computing with Resistive Switching Devices.
Resistive switches, commonly referred to as resistive memory (RRAM) devices and modeled as memristors, are an emerging nanoscale technology that can revolutionize data storage and computing approaches. Enabled by the advancement of nanoscale semiconductor fabrication and detailed understanding of the physical and chemical processes occurring at the atomic scale, resistive switches offer high speed, low-power, and extremely dense nonvolatile data storage. Further, the analog capabilities of resistive switching devices enables neuromorphic computing approaches which can achieve massively parallel computation with a power and area budget that is orders of magnitude lower than today’s conventional, digital approaches.
This dissertation presents the investigation of tungsten oxide based resistive switching devices for use in neuromorphic computing applications. Device structure, fabrication, and integration are described and physical models are developed to describe the behavior of the devices. These models are used to develop array-scale simulations in support of neuromorphic computing approaches. Several signal processing algorithms are adapted for acceleration using arrays of resistive switches. Both simulation and experimental results are reported. Finally, guiding principles and proposals for future work are discussed.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/116743/1/sheridp_1.pd
Emulating long-term synaptic dynamics with memristive devices
The potential of memristive devices is often seeing in implementing
neuromorphic architectures for achieving brain-like computation. However, the
designing procedures do not allow for extended manipulation of the material,
unlike CMOS technology, the properties of the memristive material should be
harnessed in the context of such computation, under the view that biological
synapses are memristors. Here we demonstrate that single solid-state TiO2
memristors can exhibit associative plasticity phenomena observed in biological
cortical synapses, and are captured by a phenomenological plasticity model
called triplet rule. This rule comprises of a spike-timing dependent plasticity
regime and a classical hebbian associative regime, and is compatible with a
large amount of electrophysiology data. Via a set of experiments with our
artificial, memristive, synapses we show that, contrary to conventional uses of
solid-state memory, the co-existence of field- and thermally-driven switching
mechanisms that could render bipolar and/or unipolar programming modes is a
salient feature for capturing long-term potentiation and depression synaptic
dynamics. We further demonstrate that the non-linear accumulating nature of
memristors promotes long-term potentiating or depressing memory transitions
Cryogenic Neuromorphic Hardware
The revolution in artificial intelligence (AI) brings up an enormous storage
and data processing requirement. Large power consumption and hardware overhead
have become the main challenges for building next-generation AI hardware. To
mitigate this, Neuromorphic computing has drawn immense attention due to its
excellent capability for data processing with very low power consumption. While
relentless research has been underway for years to minimize the power
consumption in neuromorphic hardware, we are still a long way off from reaching
the energy efficiency of the human brain. Furthermore, design complexity and
process variation hinder the large-scale implementation of current neuromorphic
platforms. Recently, the concept of implementing neuromorphic computing systems
in cryogenic temperature has garnered intense interest thanks to their
excellent speed and power metric. Several cryogenic devices can be engineered
to work as neuromorphic primitives with ultra-low demand for power. Here we
comprehensively review the cryogenic neuromorphic hardware. We classify the
existing cryogenic neuromorphic hardware into several hierarchical categories
and sketch a comparative analysis based on key performance metrics. Our
analysis concisely describes the operation of the associated circuit topology
and outlines the advantages and challenges encountered by the state-of-the-art
technology platforms. Finally, we provide insights to circumvent these
challenges for the future progression of research
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