5nm 이하 3D Transistors의 Self-Heating 및 전열특성분석 연구

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·컴퓨터공학부, 2021.8. 신형철.In this thesis, Self-Heating Effect (SHE) is investigated using TCAD simulations in various Sub-10-nm node Field Effect Transistor (FET). As the node decreases, logic devices have evolved into 3D MOSFET structures from Fin-FET to Nanosheet-FET. In the case of 3D MOSFET, there are thermal reliability issues due to the following reasons: ⅰ) The power density of the channel is high, ⅱ) The channel structure surrounded by SiO2, ⅲ) The overall low thermal conductivity characteristics due to scaling down. Many papers introduce the analysis and prediction of temperature rise by SHE in the device, but there are no papers presenting the content of mitigation of temperature rise. Therefore, we have studied the methods of decreasing the maximum lattice temperature (TL,max) such as shallow trench isolation (STI) composition engineering in Fin-FET, thermal analysis according to DC/AC/duty cycle in nanowire-FET, and active region ( e.g., gate metal thickness, channel width, channel number etc..) optimization in nanosheet-FET. In addition, lifetime affected by hot carrier injection (HCI) / bias-temperature instability (BTI) is also analyzed according to various thermal relaxation methods presented.이 논문에서는 다양한 Sub-10nm 노드 전계 효과 트랜지스터 (FET)에서 TCAD 시뮬레이션을 사용하여 자체 발열 효과 (SHE)를 조사합니다. 노드가 감소함에 따라 논리 장치는 Fin-FET에서 Nanosheet-FET로 3D MOSFET 구조로 진화했습니다. 3D MOSFET의 경우 ⅰ) 채널의 전력 밀도가 높음, ⅱ) SiO2로 둘러싸인 채널 구조, ⅲ) 축소로 인해 전체적으로 낮은 열전도 특성 등 다음과 같은 이유로 열 신뢰성 문제가 있습니다. 한편, 많은 논문이 device에서 SHE에 의한 온도 상승의 분석 및 예측을 소개하지만 온도 상승 완화의 내용을 제시하는 논문은 거의 없습니다. 따라서 Fin-FET의 STI (Shallow Trench Isolation) 구성 공학, nanowire-FET의 DC / AC / 듀티 사이클에 따른 열 분석, nanosheet-FET에서 소자의 중요영역(예: 게이트 금속 두께, 채널 폭, 채널 번호 등)의 최적화를 통해서 최대 격자 온도 (TL,max)를 낮추는 방법등을 연구했습니다. 또한 더 나아가서 HCI (Hot Carrier Injection) / BTI (Bias-Temperature Instability)의 영향을 받는 수명도 제시된 다양한 열 완화 방법에 따라 분석하여 소자의 제작에 있어 열적 특성과 수명을 좋게 만드는 지표를 제시합니다 .Chapter 1 Introduction 1 1.1. Development of Semconductor structure 1 1.2. Self-Heating Effect issues in semiconductor devices 3 Chapter 2 Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing Ioff in Various Sub-10-nm 3-D Transistor 7 2.1. Introduction 7 2.2. Device Structure and Simulation Condition 7 2.3. Results and Discussion 12 2.4. Summary 27 Chapter 3 Analysis of Self Heating Effect in DC/AC Mode in Multi-channel GAA-Field Effect Transistor 32 3.1. Introduction 32 3.2. Multi-Channel Nanowire FET and Back End Of Line 33 3.3. Work Flow and Calibration Process 35 3.4. More Detailed Thermal Simulation of Nanowire-FET 37 3.5. Performance Analysis by Number of Channels 38 3.6. DC Characteristic of SHE in Nanowire-FETs 40 3.7. AC Characteristics of SHE in Nanowire-FETs 43 3.8. Summary 51 Chapter 4 Self-Heating and Electrothermal Properties of Advanced Sub-5-nm node Nanoplate FET 56 4.1. Introduction 56 4.2. Device Structure and Simulation Condition 57 4.3. Thermal characteristics by channel number and width 62 4.4. Thermal characteristics by inter layer-metal thickness (TM) 64 4.5. Life Time Prediction 65 4.6. Summary 67 Chapter 5 Study on Self Heating Effect and life time in Vertical-channel Field Effect Transistor 72 5.1. Introduction 72 5.2. Device Structure and Simulation Condition 72 5.3. Temperature and RTH according to channel width(TW) 76 5.4. Thermal properties according to air spacers and air gap 77 5.5. Ion boosting according to Channel numbers 81 5.6. Temperature imbalance of multi-channel VFETs 82 5.7. Mitigation of the channel temperature imbalance 86 5.8. Life time depending on various analysis conditions 88 5.9. Summary 89 Chapter 6 Conclusions 93 Appendix A. A Simple and Accurate Modeling Method of Channel Thermal Noise Using BSIM4 Noise Models 95 A.1. Introduction 95 A.2. Overall Schematic of the RF MOSFET Model 97 A.3. Verification of the DC Characteristics of the RF MOSFET Model 98 A.4. Verification of the MOSFET Model with Measured Y-parameters 100 A.5. Verification of the MOSFET Model with Measured Noise Parameters 101 A.6. Thermal Noise Extraction and Modeling (TNOIMOD = 0) 103 A.7. Verification of the Enhanced Model with Noise Parameters 112 A.8. Holistic Model (TNOIMOD = 1) 114 A.9. Evaluation the validity of the model for drain bias 115 A.10. Conclusion 117 Abstract in Korean 122박

Thermal Management in Fine-Grained 3-D Integrated Circuits

For beyond 2-D CMOS logic, various 3-D integration approaches specially transistor based 3-D integrations such as monolithic 3-D [1], Skybridge [2], SN3D [3] holds most promise. However, such 3D architectures within small form factor increase hotspots and demand careful consideration of thermal management at all levels of integration [4] as stacked transistors are detached from the substrate (i.e., heat sink). Traditional system level approaches such as liquid cooling [5], heat spreader [6], etc. are inadequate for transistor level 3-D integration and have huge cost overhead [7]. In this paper, we investigate the thermal profile for transistor level 3-D integration approaches through finite element based modeling. Additionally, we propose generic physical level heat management features for such transistor level 3-D integration and show their application through detailed thermal modeling and simulations. These features include a thermal junction and heat conducting nano pillar. The heat junction is a specialized junction to extract heat from a selected region in 3-D; it allows heat conduction without interference with the electrical activities of the circuit. In conjunction with the junction, our proposed thermal pillars enable heat dissipation through the substrate; these pillars are analogous to TSVs/Vias, but carry only heat. Such structures are generic and is applicable to any transistor level 3-D integration approaches. We perform 3-D finite element based analysis to capture both static and transient thermal behaviors of 3-D circuits, and show the effectiveness of heat management features. Our simulation results show that without any heat extraction feature, temperature for 3-D integrated circuits increased by almost 100K-200K. However, proposed heat extraction feature is very effective in heat management, reducing temperature from heated area by up to 53%.Comment: 9 Page

Modelling and simulation study of NMOS Si nanowire transistors

Nanowire transistors (NWTs) represent a potential alternative to Silicon FinFET technology in the 5nm CMOS technology generation and beyond. Their gate length can be scaled beyond the limitations of FinFET gate length scaling to maintain superior off-state leakage current and performance thanks to better electrostatic control through the semiconductor nanowire channels by gate-all-around (GAA) architecture. Furthermore, it is possible to stack nanowires to enhance the drive current per footprint. Based on these considerations, vertically-stacked lateral NWTs have been included in the latest edition of the International Technology Roadmap for Semiconductors (ITRS) to allow for further performance enhancement and gate pitch scaling, which are key criteria of merit for the new CMOS technology generation. However, electrostatic confinement and the transport behaviour in these devices are more complex, especially in or beyond the 5nm CMOS technology generation. At the heart of this thesis is the model-based research of aggressively-scaled NWTs suitable for implementation in or beyond the 5nm CMOS technology generation, including their physical and operational limitations and intrinsic parameter fluctuations. The Ensemble Monte Carlo approach with Poisson-Schrödinger (PS) quantum corrections was adopted for the purpose of predictive performance evaluation of NWTs. The ratio of the major to the minor ellipsoidal cross-section axis (cross-sectional aspect ratio - AR) has been identified as a significant contributing factor in device performance. Until now, semiconductor industry players have carried out experimental research on NWTs with two different cross-sections: circular cylinder (or elliptical) NWTs and nanosheet (or nanoslab) NWTs. Each version has its own benefits and drawbacks; however, the key difference between these two versions is the cross-sectional AR. Several critical design questions, including the optimal NWT cross-sectional aspect ratio, remain unanswered. To answer these questions, the AR of a GAA NWT has been investigated in detail in this research maintaining the cross-sectional area constant. Signatures of isotropic charge distributions within Si NWTs were observed, exhibiting the same attributes as the golden ratio (Phi), the significance of which is well-known in the fields of art and architecture. To address the gap in the existing literature, which largely explores NWT scaling using single-channel simulation, thorough simulations of multiple channels vertically-stacked NWTs have been carried out with different cross-sectional shapes and channel lengths. Contact resistance, non-equilibrium transport and quantum confinement effects have been taken into account during the simulations in order to realistically access performance and scalability. Finally, the individual and combined effects of key statistical variability (SV) sources on threshold voltage (VT), subthreshold slope (SS), ON-current (Ion) and drain-induced barrier lowering (DIBL) have been simulated and discussed. The results indicate that the variability of NWTs is impacted by device architecture and dimensions, with a significant reduction in SV found in NWTs with optimal aspect ratios. Furthermore, a reduction in the variability of the threshold voltage has been observed in vertically-stacked NWTs due to the cancelling-out of variability in double and triple lateral channel NWTs

DESIGN, MODELING, OPTIMIZATION, AND BENCHMARKING OF INTERCONNECTS AND SCALING TECHNOLOGIES AND THEIR CIRCUIT AND SYSTEM LEVEL IMPACT

This research focuses on the future of integrated circuit (IC) scaling technologies at the device and back end of line (BEOL) level. This work includes high level modeling of different technologies and quantifying potential performance gains on a circuit and system level. From the device side, this research looks at the scaling challenges and the future scaling drivers for conventional charge-based devices implemented at the 7nm technology node and beyond. It examines the system-level performance of stacking device logic in addition to tunneling field effect transistors (TFET) and their potential as beyond-CMOS devices. Finally, this research models and benchmarks BEOL scaling challenges and evaluates proposed technological advancements such as metal barrier scaling for copper interconnects and replacing local interconnects with ruthenium. Potential impact on performance, power, and area of these interconnect technologies is quantified for fully placed and routed circuits.Ph.D

Polarity Control at Runtime:from Circuit Concept to Device Fabrication

Semiconductor device research for digital circuit design is currently facing increasing challenges to enhance miniaturization and performance. A huge economic push and the interest in novel applications are stimulating the development of new pathways to overcome physical limitations affecting conventional CMOS technology. Here, we propose a novel Schottky barrier device concept based on electrostatic polarity control. Specifically, this device can behave as p- or n-type by simply changing an electric input bias. This device combines More-than-Moore and Beyond CMOS elements to create an efficient technology with a viable path to Very Large Scale Integration (VLSI). This thesis proposes a device/circuit/architecture co-optimization methodology, where aspects of device technology to logic circuit and system design are considered. At device level, a full CMOS compatible fabrication process is presented. In particular, devices are demonstrated using vertically stacked, top-down fabricated silicon nanowires with gate-all-around electrode geometry. Source and drain contacts are implemented using nickel silicide to provide quasi-symmetric conduction of either electrons or holes, depending on the mode of operation. Electrical measurements confirm excellent performance, showing Ion/Ioff > 10^7 and subthreshold slopes approaching the thermal limit, SS ~ 60mV/dec (~ 63mV/dec) for n(p)-type operation in the same physical device. Moreover, the shown devices behave as p-type for a polarization bias (polarity gate voltage, Vpg) of 0V, and n-type for a Vpg = 1V, confirming their compatibility with multi-level static logic circuit design. At logic gate level, two- and four-transistor logic gates are fabricated and tested. In particular, the first fully functional, two-transistor XOR logic gate is demonstrated through electrical characterization, confirming that polarity control can enable more compact logic gate design with respect to conventional CMOS. Furthermore, we show for the first time fabricated four- transistors logic gates that can be reconfigured as NAND or XOR only depending on their external connectivity. In this case, logic gates with full swing output range are experimentally demonstrated. Finally, single device and mixed-mode TCAD simulation results show that lower Vth and more optimized polarization ranges can be expected in scaled devices implementing strain or high-k technologies. At circuit and system level, a full semi-custom logic circuit design tool flow was defined and configured. Using this flow, novel logic libraries based on standard cells or regular gate fabrics were compared with standard CMOS. In this respect, results were shown in comparison to CMOS, including a 40% normalized area-delay product reduction for the analyzed standard cell libraries, and improvements of over 2× in terms of normalized delay for regular Controlled Polarity (CP)-based cells in the context of Structured ASICs. These results, in turn, confirm the interest in further developing and optimizing CP devices, as promising candidates for future digital circuit technology

Charge-based compact model of gate-all-around floating gate nanowire with variable oxide thickness for flash memory cell

Due to high gate electrostatic control and introduction of punch and plug process technology, the gate-all-around (GAA) transistor is very promising in, and apparently has been utilized for, flash memory applications. However, GAA Floating Gate (GAA-FG) memory cell still requires high programming voltage that may be susceptible to cell-to-cell interference. Scaling down the tunnel oxide can reduce the Program/Erase (P/E) voltage but degrades the data retention capability. By using Technology-Computer-Aided-Design (TCAD) tools, the concept of tunnel barrier engineering using Variable Oxide Thickness (VARIOT) of low-k/high-k stack is utilized in compensating the trade-off between P/E operation and retention characteristics. Four high-k dielectrics (Si3N4, Al2O3, HfO2 and ZrO2) that are commonly used in semiconductor process technology are examined with SiO2 as its low-k dielectric. It is found that by using SiO2/Al2O3 as the tunnel layer, both the P/E and retention characteristics of GAA-FG can be compensated. About 30% improvement in memory window than conventional SiO2 is obtained and only 1% of charge-loss is predicted after 10 years of applying gate stress of -3.6V. Compact model of GAA-FG is initiated by developing a continuous explicit core model of GAA transistor (GAA Nanowire MOSFET (GAANWFET) and Juntionless Nanowire Transitor (JNT)). The validity of the theory and compact model is identified based on sophisticated numerical TCAD simulator for under 10% maximum error of surface potential. It is revealed that with the inclusion of partial-depletion conduction, the accuracy of the core model for GAANWFET is improved by more than 50% in the subthreshold region with doping-geometry ratio can be as high as about 0.86. As for JNT, despite the model being accurate for doping-geometry ratio upto 0.6, it is also independent of fitting parameters that may vary under different terminal biases or doping-geometry cases. The compact model of GAA-FG is completed by incorperating Charge Balance Model (CBM) into GAA transistor core model where good agreement is obtained with TCAD simulation and published experimental work. The CBM gives better accuracy than the conventional capacitive coupling approach under subthreshold region with approximately 10% error of floating gate potential. Therefore, the proposed compact model can be used to assist experimental work in extracting experimental data

Challenges and solutions for large-scale integration of emerging technologies

Title from PDF of title page viewed June 15, 2021Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (pages 67-88)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021The semiconductor revolution so far has been primarily driven by the ability to shrink devices and interconnects proportionally (Moore's law) while achieving incremental benefits. In sub-10nm nodes, device scaling reaches its fundamental limits, and the interconnect bottleneck is dominating power and performance. As the traditional way of CMOS scaling comes to an end, it is essential to find an alternative to continue this progress. However, an alternative technology for general-purpose computing remains elusive; currently pursued research directions face adoption challenges in all aspects from materials, devices to architecture, thermal management, integration, and manufacturing. Crosstalk Computing, a novel emerging computing technique, addresses some of the challenges and proposes a new paradigm for circuit design, scaling, and security. However, like other emerging technologies, Crosstalk Computing also faces challenges like designing large-scale circuits using existing CAD tools, scalability, evaluation and benchmarking of large-scale designs, experimentation through commercial foundry processes to compete/co-exist with CMOS for digital logic implementations. This dissertation addresses these issues by providing a methodology for circuit synthesis customizing the existing EDA tool flow, evaluating and benchmarking against state-of-the-art CMOS for large-scale circuits designed at 7nm from MCNC benchmark suits. This research also presents a study on Crosstalk technology's scalability aspects and shows how the circuits' properties evolve from 180nm to 7nm technology nodes. Some significant results are for primitive Crosstalk gate, designed in 180nm, 65nm, 32nm, and 7nm technology nodes, the average reduction in power is 42.5%, and an average improvement in performance is 34.5% comparing to CMOS for all mentioned nodes. For benchmarking large-scale circuits designed at 7nm, there are 48%, 57%, and 10% improvements against CMOS designs in terms of density, power, and performance, respectively. An experimental demonstration of a proof-of-concept prototype chip for Crosstalk Computing at TSMC 65nm technology is also presented in this dissertation, showing the Crosstalk gates can be realized using the existing manufacturing process. Additionally, the dissertation also provides a fine-grained thermal management approach for emerging technologies like transistor-level 3-D integration (Monolithic 3-D, Skybridge, SN3D), which holds the most promise beyond 2-D CMOS technology. However, such 3-D architectures within small form factors increase hotspots and demand careful consideration of thermal management at all integration levels. This research proposes a new direction for fine-grained thermal management approach for transistor-level 3-D integrated circuits through the insertion of architected heat extraction features that can be part of circuit design, and an integrated methodology for thermal evaluation of 3-D circuits combining different simulation outcomes at advanced nodes, which can be integrated to traditional CAD flow. The results show that the proposed heat extraction features effectively reduce the temperature from a heated location. Thus, the dissertation provides a new perspective to overcome the challenges faced by emerging technologies where the device, circuit, connectivity, heat management, and manufacturing are addressed in an integrated manner.Introduction and motivation -- Cross talk computing overview -- Logic simplification approach for Crosstalk circuit design -- Crostalk computing scalability study: from 180 nm to 7 nm -- Designing large*scale circuits in Crosstalk at 7 nm -- Comparison and benchmarking -- Experimental demonstration of Crosstalk computing -- Thermal management challenges and mitigation techniques for transistor-level- 3D integratio

적층 나노시트 구조의 음의 정전용량 전계 효과 트랜지스터

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 최우영.The development of integrated circuit (IC) technology has continued to improve speed and capacity through miniaturization of devices. However, power density is increasing rapidly due to the increasing leakage current as miniaturization advances. Although the remarkable advancement of process technology has allowed complementary-metal-oxide-semiconductor (CMOS) technology to consistently overcome its constraints, the physical limitations of the metal-oxide-semiconductor field-effect transistor (MOSFET) are unmanageable. Accordingly, research on logic device is being divided into a CMOS-extension and a beyond-CMOS. CMOS-extension focuses on the gate-all-around field-effect transistors (GAAFETs) which is a promising architecture for future CMOS thanks to the excellent electrostatic gate controllability. Particularly, nanosheet (NS) architecture with high current drivability required in ICs, is the most promising. However, NS GAAFET has a trade-off relation between the controllability and the drivability, which requires the necessity of a higher-level effective oxide thickness (EOT) scaling for further scaling of NS GAAFET. On the other hand, beyond-CMOS mainly focuses on developing devices with novel mechanisms to overcome the MOSFETs' physical limits. Among several candidates, negative capacitance field-effect transistors (NCFETs) with exceptional CMOS compatibility and current drivability are highlighted as future logic devices for low-power, high-performance operation. Although the NCFET utilizing the negative capacitance (NC) effect of a ferroelectric has been demonstrated theoretically by the Landau model, it is challenging to be implemented due to the fact that stabilized NC and sub-thermionic subthreshold swing (SS) are incompatible. In this dissertation, a GAA NCFET that maintains a stable capacitance boosting by NC effect and exhibits high performance is demonstrated. A ferroelectric-antiferroelectric mixed-phase hafnium-zirconium-oxide (HZO) thin film was introduced, whose effect was confirmed by capacitors and FET experiments. Furthermore, the mixed-phase HZO was demonstrated on a stacked nanosheet gate-all-around (stacked NS GAA) structure, the advanced CMOS technology, which exhibits a superior gate controllability as well as a satisfactory drivability for ICs. The hysteresis-free stable NC operation with the superior performance was confirmed in NS GAA NCFET. The improved SS and on-current (Ion) compared to MOSFETs fabricated in the same manner were validated, and its feasibility as a low-power, high-performance logic device was proven based on a variety of figure of merits.집적회로 기술의 발전은 소자의 소형화를 통한 속도 및 용량의 향상을 위해 발전을 거듭해왔다. 그러나 소형화를 거듭할수록 증가하는 누설전류의 문제로 전력 밀도가 급격하게 증가하고 있다. 상보형 금속-산화막-반도체(CMOS) 기술은 눈부신 공정기술의 성장에 힘입어 한계를 끊임없이 극복해왔으나, 기존의 금속-산화막-반도체 전계-효과-트랜지스터(MOSFET)의 물리적 한계는 극복할 수 없는 문제이다. 이에 따라 논리 반도체에 관한 연구는 CMOS를 연장하는 방향과 CMOS를 뛰어넘는 방향으로 나뉘어 진행되고 있다. CMOS를 연장하는 방향은 뛰어난 정전기적 게이트 장악력을 갖는 차세대 CMOS 구조로 유망한 게이트-올-어라운드 전계-효과-트랜지스터(GAAFET)에 관한 연구가 주를 이룬다. 특히 높은 전류 구동력을 가질 수 있는 나노시트(NS) 구조가 가장 유망한데, 게이트 장악력이 전류 구동력과 상충된다는 단점이 있다. 이에 따라 NS GAAFET 기술을 위해서는 더 높은 수준의 유효산화막두께 (EOT) 스케일링이 필수적이다. 한편, CMOS를 뛰어넘는 방향의 연구는 MOSFET의 물리적 한계를 극복하기 위해 새로운 메커니즘을 갖는 소자를 개발하는 방향으로 이루어진다. 다양한 후보군 중 CMOS 호환성과 전류 구동능력이 뛰어난 음의 정전용량 전계-효과-트랜지스터(NCFET)이 저전력, 고성능 동작을 위한 미래 CMOS 소자로 각광받고 있다. 강유전체의 음의 정전용량 (NC) 효과를 이용한 NCFET은 Landau 모델에 의해 이론적으로 증명되었으나, 열역학적으로 안정한 상태와 60 mV/dec 이하의 문턱전압-이하-기울기(SS)를 동시에 구현하기 불가능하다는 문제가 있다. 본 학위논문에서는 안정한 정전용량 향상 특성을 가지며 높은 성능을 갖는 NS GAA NCFET을 구현하였다. 강유전체(ferroelectric)-반강유전체(antiferroelectric) 혼합상(mixed-phase) 하프늄-지르코늄-옥사이드(HZO) 박막의 정전용량 향상 효과를 커패시터 및 FET 제작을 통해 효과를 검증하였다. 또한 높은 게이트 장악력을 가지며 집적회로에서 요구하는 전류 구동력을 만족시킬 수 있는 적층형 나노시트 게이트-올-어라운드(stacked NS GAA) 구조에 혼합상 NC 박막을 적용한 FET을 시연하고 성능의 우수성을 확인하였다. 동일하게 제작된 MOSFET 대비 향상된 SS와 구동 전류(Ion)를 확인하였고, 다양한 성능 지수를 토대로 저전력, 고성능 로직 소자로서의 타당성을 검증하였다.Abstract i Contents iv List of Table vii List of Figures viii Chapter 1 Introduction 1 1.1 Power and Area Scaling Challenges 1 1.2 Nanosheet Gate-All-Around FETs 5 1.2.1 Gate-All-Around FETs 5 1.2.2 Nanosheet GAAFETs 6 1.3 Negative Capacitance FETs 11 1.3.1 Negative Capacitance in Ferroelectric Materials 11 1.3.2 Negative Capacitance for Steep Switching Devices 14 1.3.3 Stable NC vs. Sub-thermionic SS 17 1.4 Scope and Organization of Dissertation 21 Chapter 2 Stacked NS GAA NCFET with Ferroelectric-Antiferroelectric-Mixed-Phase HZO 22 2.1 Mixed-Phase HZO for Capacitance Boosting 22 2.2 NS GAA NCFET using Mixed-Phase HZO 25 Chapter 3 HZO ALD Stack Optimization 28 3.1 Metal-Ferroelectric-Interlayer-Silicon (MFIS) / MFM Capacitors 29 3.1.1 Fabrication of MFIS Capacitors 29 3.1.2 Electrical Characteristics of MFIS / MFM Capacitors 33 3.2 SOI Planar NCFETs 38 3.2.1 DC Measurements 38 3.2.2 Direct Capacitance Measurements 47 3.2.3 Speed Measurements 49 Chapter 4 Device Fabrication of Stacked NS GAA NCFET 51 4.1 Initial Process Flow of NS GAA NCFET 52 4.2 Process Issues and Solution 56 4.2.1 External Resistance 56 4.2.2 TiN Gate Sidewall Spacer 60 4.2.3 Unintentionally Etched Sacrificial Layer 65 4.2.4 Discussions 68 4.3 Channel Release Process 69 4.3.1 Consideration in Channel Release Process 69 4.3.2 Methods for SiGe Selective Etching 72 4.3.3 SiGe Selective Etching using Carboxylic Acid Solution 75 4.4 Revised Process of NS GAA NCFET 78 Chapter 5 Electrical Characteristics of Fabricated NS GAA NCFET 84 5.1 DC Characteristics 85 5.1.1 NS GAA NCFET vs. Planar SOI NCFET 85 5.1.2 Performance Enhancement of NS GAA NCFET 88 5.1.3 Performance Evaluation 96 5.2 Operating Temperature Properties 99 Chapter 6 Conclusion 102 Bibliography 105 초 록 115박