2,021 research outputs found

    Design, processing and testing of LSI arrays hybrid microelectronics task

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    Those factors affecting the cost of electronic subsystems utilizing LSI microcircuits were determined and the most efficient methods for low cost packaging of LSI devices as a function of density and reliability were developed

    Copper to copper bonding by nano interfaces for fine pitch interconnections and thermal applications

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    Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law at IC level and system miniaturization with System-On-Package (SOP) paradigm at system level, have resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. However, system miniaturization poses several electrical and thermal challenges that demand innovative solutions including advanced materials, bonding and assembly techniques. Heterogeneous material and device integration for thermal structures and IC assembly are limited by the bonding technology and the electrical and thermal impedance of the bonding interfaces. Solder - based bonding technology that is prevalent today is a major limitation to future systems. The trend towards miniaturized systems is expected to drive downscaling of IC I/O pad pitches from 40µm to 1- 5µm in future. Solder technology imposes several pitch, processability and cost restrictions at such fine pitches. Furthermore, according to International Technology Roadmap for Semiconductors (ITRS-2006), the supply current in high performance microprocessors is expected to increase to 220 A by 2012. At such supply current, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer sized technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Similarly, thermal power dissipation is growing to unprecedented high with a projected power of 198 W by 2008 (ITRS 2006). Present thermal interfaces are not adequate for such high heat dissipation. Recently, copper based thin film bonding has become a promising approach to address the abovementioned challenges. However, copper-copper direct bonding without using solders has not been studied thoroughly. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. Hence, there is a need to develop a novel low temperature copper to copper bonding process. In the present study, nanomaterials - based copper-to-copper bonding is explored and developed as an alternative to solder-based bonding. To demonstrate fine pitch bonding, the patterning of these nanoparticles is crucial. Therefore, two novel self-patterning techniques based on: 1.) Selective wetting and 2.) Selective nanoparticle deposition, are developed to address this challenge. Nanoparticle active layer facilitates diffusion and, thus, a reliable bond can be achieved using less thermal budget. Quantitative characterization of the bonding revealed good metallurgical bonding with very high bond strength. This has been confirmed by several morphological and structural characterizations. A 30-micron pitch IC assembly test vehicle is used to demonstrate fine pitch patternability and bonding. In conclusion, novel nanoparticle synthesis and patterning techniques were developed and demonstrated for low-impedance and low-cost electrical and thermal interfaces.M.S.Committee Chair: Rao R. Tummala; Committee Member: C. P. Wong; Committee Member: P. M. Ra

    Developing the knowledge-based human resources that support the implementation of the National Dual Training System (NDTS): evaluation of TVET teacher's competency at MARA Training Institutions

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    Development in the world of technical and vocational education and training (TVET) on an ongoing basis is a challenge to the profession of the TVET-teachers to maintain their performance. The ability of teachers to identify the competencies required by their profession is very critical to enable them to make improvements in teaching and learning. For a broader perspective the competency needs of the labour market have to be matched by those developed within the vocational learning processes. Consequently, this study has focused on developing and validating the new empirical based TVET-teacher competency profile and evaluating teacher’s competency. This study combines both quantitative and qualitative research methodology that was designed to answer all the research questions. The new empirical based competency profile development and TVET-teacher evaluation was based upon an instructional design model. In addition, a modified Delphi technique has also been adopted throughout the process. Initially, 98 elements of competencies were listed by expert panel and rated by TVET institutions as important. Then, analysis using manual and statistical procedure found that 112 elements of competencies have emerged from seventeen (17) clusters of competencies. Prior to that, using the preliminary TVET-teacher competency profile, the level of TVETteacher competencies was found to be Proficient and the finding of 112 elements of competencies with 17 clusters was finally used to develop the new empirical based competency profile for MARA TVET-teacher. Mean score analysis of teacher competencies found that there were gaps in teacher competencies between MARA institutions (IKM) and other TVET institutions, where MARA-teacher was significantly better than other TVET teacher. ANOVA and t-test analysis showed that there were significant differences between teacher competencies among all TVET institutions in Malaysia. On the other hand, the study showed that teacher’s age, grade and year of experience are not significant predictors for TVET-teacher competency. In the context of mastering the competency, the study also found that three competencies are classified as most difficult or challenging, twelve competencies are classified as should be improved, and eight competencies are classified as needed to be trained. Lastly, to make NDTS implementation a reality for MARA the new empirical based competency profile and the framework for career development and training pathway were established. This Framework would serve as a significant tool to develop the knowledge based human resources needed. This will ensure that TVET-teachers at MARA are trained to be knowledgeable, competent, and professional and become a pedagogical leader on an ongoing basis towards a world class TVET-education system

    Glass multilayer bonding for high density interconnect substrates

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    The aim of this research was the investigation of bonding borosilicate glass sheets, its trade mark CMZ, 100μm thickness, to create multilayer substrates capable of supporting high-density electrical interconnections. CMZ glass was chosen as it has a coefficient of thermal expansion that is close to that of silicon, thereby minimising thermal stresses in assemblies generated by manufacturing processes or service conditions. Two different methods of bonding the glass were used in this study; pressure assisted low temperature bonding (PALTB), and water glass bonding, using Sodium Trisilicate (Na2Si3O7) solution. These two bonding methods have already been applied in electronics manufacturing applications, such as silicon wafer bonding and multichip modules (MCMs). However, glass-to-glass bonding is a relatively new subject and this study is an attempt to standardise bonding processes. Additionally, the concept of using glass as a multilayer substrate provides a foundation for further exploration by other investigators. Initial tests that were carried out before standardising the procedures for these two methods showed that a two-stage bonding process provided optimum results. A preliminary stage commenced by placing the cleaned (using Decon 90 solution) samples in a vacuum oven for 15 minutes, then heating at 100oC for 1hr. The permanent stage was then achieved by heating the samples in a conventional oven at temperatures from 200 to 400oC, for different periods. At this stage, the main difference between the two methods was the application of pressure (1-2MPa) during heating of the PALTB samples. To evaluate the quality of the bonds, qualitative tests such as visual, optical microscope and dye penetrant were used. In addition, to estimate the strength and the rigidity of the interlayer bonds, two quantitative tests, comprising of deflection under cyclic stresses and crack opening were used. Thermal cycling and humidity tests were also used to assess resistance of the bonds to environmental effects. The results showed that heating to 100oC was insufficient to enhance the bonds, as occasionally a sudden increase of deflection was observed indicating slippage/delamination. These bonds were enhanced during the permanent bonding stage by heating to 300oC in PALTB, under a pressure of 1-2MPa. The crack-opening test showed that the delamination distances of the bonds in the permanent stage were lower than that for preliminary bonding in both bonding methods. The delamination distances from the crack opening tests were used to calculate the strain energy release rate (GIC) and fracture toughness (KIC) values of the interlayers. The results showed that the KIC values of the permanent PALTB and water glass interlayers were higher than 1MPa.m0.5, while the KIC value of the CMZ glass, determined by linear elastic fracture mechanics, was around 0.8MPa.m0.5. The optical observations revealed that the prepared bonded sheets did not delaminate or break after thermal cycling and humidity tests

    3D advanced integration technology for heterogeneous systems

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    International audience3D integration technology is nowadays mature enough, offering today further system integration using heterogeneous technologies, with already many different industrial successes (Imagers, 2.5D Interposers, 3D Memory Cube, etc.). CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, µ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this paper, a short overview of some recent advanced 3D technology results is presented, including some latest 3D circuit's description

    Heterogeneous 2.5D integration on through silicon interposer

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    © 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

    Thermo-Mechanical Reliability and Electrical Performance of Indium Interconnects and Under Bump Metallization

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    This thesis presents reliability analysis of indium interconnects and Under Bump Metallization (UBM) in flip chip devices. Flip chip assemblies with the use of bump interconnections are frequently used, especially in high density, three-dimensional electronic devices. Currently there are many methods for interconnect bumping, all of which require UBM. The UBM is required for interconnection, diffusion resistance and quality electrical contact between substrate and device. Bonded silicon test vehicles were comprised of Indium bumps and three UBM compositions: Ti/Ni/Au (200\xc5/1000\xc5/500\xc5), Ti/Ni (200\xc5/1000\xc5), Ni (1000\xc5). UBM and indium were deposited by evaporation and exposed to unbiased accelerated temperature cycling(-55°C to 125°C, 15°C/min ramp rate). Finite Element Analysis (FEA) simulations were used to gain understanding of non-linear strain behavior of indium interconnects during temperature cycling. Experimental testing coupled with FEA simulations facilitated cycle-to-failure calculations. FEA results show plastic strain concentrations within indium bump below failure limits. It has been demonstrated that fabrication of Ti/Ni/Au, Ti/Ni, and Ni UBM stacks performed reliably within infant mortality failure region

    Advances in panel glass packaging of mems and sensors for low stress and near hermetic reliability

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    MEMS based sensing is gaining widespread adoption in consumer electronics as well as the next generation Internet of Things (IoT) market. Such applications serve as primary drivers towards miniaturization for increased component density, multi-chip integration, lower cost and better reliability. Traditional approaches like System-on-Chip (SoC) and System on Board (SoB) are not ideal to address these challenges and there is a need to find solutions at package level, through heterogeneous package integration (HPI). However, existing MEMS packaging techniques like laminate/ceramic substrate packaging and silicon wafer level packaging face challenges like standardization, heterogeneous package integration and form factor miniaturization. Besides, application specific packages take up the largest fraction of the total manufacturing cost. Therefore, advanced packaging of MEMS sensors for HPI plays a critical role in the short and long run towards the SOP vision. This dissertation demonstrates a low stress, reliable, near-hermetic ultra-thin glass cavity MEMS packages as a solution that combines the advantages of LTCC/laminate substrates and silicon wafer level packaging while also addressing their limitations. These glass based cavity packages can be scaled down to 2x smaller form factors (<500μm) and are fabricated out of large panel fabrication processes thereby addressing the cost and form factor requirements of MEMS packaging. Flexible cavity design, advances in through-glass via technologies and dimensional stability of thin glass also enable die stacking and 3D assembly for sensor-processor integration towards sensor fusion. The following building block technologies were explored: (a) reliable cavity formation in thin glass panels (b) low stress glass-glass bonding, and (c) high throughput, fully filled through-package-via metallization in glass. Three main technical challenges were overcome to realize the objectives: (a) glass cracking, side wall taper, side wall roughness and defects, (b) interfacial voids at glass-polymer-glass interface and (c) electrical opens and high frequency performance of copper paste filled through-package-vias in glass.M.S

    Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

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    Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra
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