258 research outputs found
Extremely Large Area (88 mm X 88 mm) Superconducting Integrated Circuit (ELASIC)
Superconducting integrated circuit (SIC) is a promising "beyond-CMOS" device
technology enables speed-of-light, nearly lossless communications to advance
cryogenic (4 K or lower) computing. However, the lack of large-area
superconducting IC has hindered the development of scalable practical systems.
Herein, we describe a novel approach to interconnect 16 high-resolution deep UV
(DUV EX4, 248 nm lithography) full reticle circuits to fabricate an extremely
large (88mm X 88 mm) area superconducting integrated circuit (ELASIC). The
fabrication process starts by interconnecting four high-resolution DUV EX4 (22
mm X 22 mm) full reticles using a single large-field (44 mm X 44 mm) I-line
(365 nm lithography) reticle, followed by I-line reticle stitching at the
boundaries of 44 mm X 44 mm fields to fabricate the complete ELASIC field (88
mm X 88 mm). The ELASIC demonstrated a 2X-12X reduction in circuit features and
maintained high-stitched line superconducting critical currents. We examined
quantum flux parametron (QFP) circuits to demonstrate the viability of common
active components used for data buffering and transmission. Considering that no
stitching requirement for high-resolution EX4 DUV reticles is employed, the
present fabrication process has the potential to advance the scaling of
superconducting quantum devices
Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies
Working for the photolithography tool manufacturer leader sometimes gives me the impression
of how complex and specific is the sector I am working on. This master thesis topic came with
the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a
helicopter view usually helps to understand where a process is in the productive chain, or what
other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico
CMUTs with integrated electronics for forward looking IVUS imaging
Issued as final reportBoston Scientific CorporationCapacitive micromachined ultrasonic transducers (cMUTs) have a great potential for implementing miniature arrays for intravascular ultrasound (IVUS) imaging. The Degertekin laboratory has recently developed cMUT manufacturing processes which enable post-CMOS fabrication of cMUT arrays for electronics integration. The purpose of this research proposal is to develop forward looking cMUT IVUS arrays and associated electronics for operation in the 10-50MHz range, and investigate the feasibility of integration of high performance cMUTs with CMOS electronics on a single silicon chip for the first time. If successful, this project will lead to low-cost forward looking IVUS imaging devices with high imaging performance and enable numerous diagnosis and therapeutic applications of IVUS
A Comprehensive Workflow for General-Purpose Neural Modeling with Highly Configurable Neuromorphic Hardware Systems
In this paper we present a methodological framework that meets novel
requirements emerging from upcoming types of accelerated and highly
configurable neuromorphic hardware systems. We describe in detail a device with
45 million programmable and dynamic synapses that is currently under
development, and we sketch the conceptual challenges that arise from taking
this platform into operation. More specifically, we aim at the establishment of
this neuromorphic system as a flexible and neuroscientifically valuable
modeling tool that can be used by non-hardware-experts. We consider various
functional aspects to be crucial for this purpose, and we introduce a
consistent workflow with detailed descriptions of all involved modules that
implement the suggested steps: The integration of the hardware interface into
the simulator-independent model description language PyNN; a fully automated
translation between the PyNN domain and appropriate hardware configurations; an
executable specification of the future neuromorphic system that can be
seamlessly integrated into this biology-to-hardware mapping process as a test
bench for all software layers and possible hardware design modifications; an
evaluation scheme that deploys models from a dedicated benchmark library,
compares the results generated by virtual or prototype hardware devices with
reference software simulations and analyzes the differences. The integration of
these components into one hardware-software workflow provides an ecosystem for
ongoing preparative studies that support the hardware design process and
represents the basis for the maturity of the model-to-hardware mapping
software. The functionality and flexibility of the latter is proven with a
variety of experimental results
Image-based EUVL Aberration Metrology
A significant factor in the degradation of nanolithographic image fidelity is optical wavefront aberration. As resolution of nanolithography systems increases, effects of wavefront aberrations on aerial image become more influential. The tolerance of such aberrations is governed by the requirements of features that are being imaged, often requiring lenses that can be corrected with a high degree of accuracy and precision. Resolution of lithographic systems is driven by scaling wavelength down and numerical aperture (NA) up. However, aberrations are also affected from the changes in wavelength and NA. Reduction in wavelength or increase in NA result in greater impact of aberrations, where the latter shows a quadratic dependence. Current demands in semiconductor manufacturing are constantly pushing lithographic systems to operate at the diffraction limit; hence, prompting a need to reduce all degrading effects on image properties to achieve maximum performance. Therefore, the need for highly accurate in-situ aberration measurement and correction is paramount. In this work, an approach has been developed in which several targets including phase wheel, phase disk, phase edges, and binary structures are used to generate optical images to detect and monitor aberrations in extreme ultraviolet (EUV) lithographic systems. The benefit of using printed patterns as opposed to other techniques is that the lithography system is tested under standard operating conditions. Mathematical models in conjunction with iterative lithographic simulations are used to determine pupil phase wavefront errors and describe them as combinations of Zernike polynomials
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