6,221 research outputs found
MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning
Placement is an essential task in modern chip design, aiming at placing
millions of circuit modules on a 2D chip canvas. Unlike the human-centric
solution, which requires months of intense effort by hardware engineers to
produce a layout to minimize delay and energy consumption, deep reinforcement
learning has become an emerging autonomous tool. However, the learning-centric
method is still in its early stage, impeded by a massive design space of size
ten to the order of a few thousand. This work presents MaskPlace to
automatically generate a valid chip layout design within a few hours, whose
performance can be superior or comparable to recent advanced approaches. It has
several appealing benefits that prior arts do not have. Firstly, MaskPlace
recasts placement as a problem of learning pixel-level visual representation to
comprehensively describe millions of modules on a chip, enabling placement in a
high-resolution canvas and a large action space. It outperforms recent methods
that represent a chip as a hypergraph. Secondly, it enables training the policy
network by an intuitive reward function with dense reward, rather than a
complicated reward function with sparse reward from previous methods. Thirdly,
extensive experiments on many public benchmarks show that MaskPlace outperforms
existing RL approaches in all key performance metrics, including wirelength,
congestion, and density. For example, it achieves 60%-90% wirelength reduction
and guarantees zero overlaps. We believe MaskPlace can improve AI-assisted chip
layout design. The deliverables are released at
https://laiyao1.github.io/maskplace
A Survey of Prediction and Classification Techniques in Multicore Processor Systems
In multicore processor systems, being able to accurately predict the future provides new optimization opportunities, which otherwise could not be exploited. For example, an oracle able to predict a certain application\u27s behavior running on a smart phone could direct the power manager to switch to appropriate dynamic voltage and frequency scaling modes that would guarantee minimum levels of desired performance while saving energy consumption and thereby prolonging battery life. Using predictions enables systems to become proactive rather than continue to operate in a reactive manner. This prediction-based proactive approach has become increasingly popular in the design and optimization of integrated circuits and of multicore processor systems. Prediction transforms from simple forecasting to sophisticated machine learning based prediction and classification that learns from existing data, employs data mining, and predicts future behavior. This can be exploited by novel optimization techniques that can span across all layers of the computing stack. In this survey paper, we present a discussion of the most popular techniques on prediction and classification in the general context of computing systems with emphasis on multicore processors. The paper is far from comprehensive, but, it will help the reader interested in employing prediction in optimization of multicore processor systems
DeepSoCS: A Neural Scheduler for Heterogeneous System-on-Chip (SoC) Resource Scheduling
In this paper, we~present a novel scheduling solution for a class of
System-on-Chip (SoC) systems where heterogeneous chip resources (DSP, FPGA,
GPU, etc.) must be efficiently scheduled for continuously arriving hierarchical
jobs with their tasks represented by a directed acyclic graph. Traditionally,
heuristic algorithms have been widely used for many resource scheduling
domains, and Heterogeneous Earliest Finish Time (HEFT) has been a dominating
state-of-the-art technique across a broad range of heterogeneous resource
scheduling domains over many years. Despite their long-standing popularity,
HEFT-like algorithms are known to be vulnerable to a small amount of noise
added to the environment. Our Deep Reinforcement Learning (DRL)-based SoC
Scheduler (DeepSoCS), capable of learning the "best" task ordering under
dynamic environment changes, overcomes the brittleness of rule-based schedulers
such as HEFT with significantly higher performance across different types of
jobs. We~describe a DeepSoCS design process using a real-time heterogeneous SoC
scheduling emulator, discuss major challenges, and present two novel neural
network design features that lead to outperforming HEFT: (i) hierarchical job-
and task-graph embedding; and (ii) efficient use of real-time task information
in the state space. Furthermore, we~introduce effective techniques to address
two fundamental challenges present in our environment: delayed consequences and
joint actions. Through an extensive simulation study, we~show that our DeepSoCS
exhibits the significantly higher performance of job execution time than that
of HEFT with a higher level of robustness under realistic noise conditions.
We~conclude with a discussion of the potential improvements for our DeepSoCS
neural scheduler.Comment: 18 pages, Accepted by Electronics 202
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