Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations

The current design and manufacturing semiconductor technologies require to test the products against delay related defects. However, complex acpSOC require low-overhead testability methods to keep the test cost at an acceptable level. Skewed-load tests seem to be the appropriate way to test delay faults in these acpSOC because the test application requires only one storage element per scan cell. Compressed skewed-load test generator based on genetic algorithm is proposed for wrapper-based logic cores of acpSOC. Deterministic population initialization is used to ensure the highest achievable aclTDF coverage for the given wrapper and scan cell order. The developed method performs test data compression by generating test vectors containing already overlapped test vector pairs. The experimental results show high fault coverages, decreased test lengths and better scalability in comparison to recent methods

Calibration of Aperture Arrays in Time Domain Using the Simultaneous Perturbation Algorithm

Online calibration is desired in antenna arrays of ultrawide bandwidth. This study proposes a time domain calibration method based on the simultaneous perturbation algorithm. Two objective functions were established: power of the received signal at array output; or combination of power and correlation coefficient between the signal at array output and a target signal. For both criteria, the convergence settings require only two measurements at each iteration. One advantage of the method is that the entire signal operation for calibration is performed in the time domain. This is achieved by resolving the effects of distortion on time delay of each channel, which accounts for both amplitude and phase distortions at different frequencies. Therefore, the proposed method significantly increased the calibration efficiency for ultra-wideband antenna arrays. Since time delay coefficients for calibration associated with array elements were determined independently due to characteristic of the simultaneous perturbation, estimation accuracy of the method is tangential to the number of elements in the array, and is mainly dependent on the convergence conditions. This gives the method an additional distinct advantage for calibrating large-scale antenna arrays with ultrawide bandwidth. An estimation accuracy of 99% on time delay adjustments has been achieved and demonstrated

Systems engineering approach to engine test stand development for micropatching evaluations

2022 Summer.Includes bibliographical references.This project applies systems engineering methodology to develop an engine test stand used to extract, patch and validate the binary file of a diesel engine electronic control module. Electronic control modules operate modern systems ranging from aircraft and spacecraft to automobiles, heavy trucks and industrial equipment. These systems are often used for decades, which may be beyond the period for which manufacturers provide support. The binary code operating these embedded controllers may need to be patched as part of maintenance or compatibility with updated requirements. The objective of this thesis is to design an evaluation system to test the extraction, patching and deployment of binary code operating an engine control module of a legacy engine platform, a Cummins 6.7L diesel engine with a Cummins CM2350 engine controller, which does not have source code available. However, through binary analysis and micropatching, it is possible to update the binary of the ECM firmware by applying a patch to change specific attributes of the operation of the ECU. To verify the results of the patch, the binary is deployed to the engine controller and the operation of the engine is assessed. An engine on a dynamometer test stand was reconfigured to be an evaluation platform for assuring non-interference attributes of the ECM binary. Requirements were identified, architecture was established, and validation was tied to corresponding test stand requirements. A method to solve an iterative numerical calculation with convergence criterion set incorrectly was implemented on the ECM, and that method was then patched with a correct convergence criterion. The evaluation system was documented for other operators to execute the evaluations

The IceCube Neutrino Observatory I: Point Source Searches

Searches for point sources of astrophysical neutrinos and related measurements: Searches for steady and time-variable sources; Follow-up programs; AGNs; GRBs; Moon shadow; Submitted papers to the 32nd International Cosmic Ray Conference, Beijing 2011.Comment: Papers submitted by the IceCube Collaboration to the 32nd International Cosmic Ray Conference, Beijing 2011; part

25 years of network access technologies: from voice to internet; the changing face of telecommunications

This work contributes to knowledge in the field of semiconductor system architectures, circuit design and implementation, and communications protocols. The work starts by describing the challenges of interfacing legacy analogue subscriber loops to an electronic circuit contained within the Central Office (Telephone Exchange) building. It then moves on to describe the globalisation of the telecom network, the demand for software programmable devices to enable system customisation cost effectively, and the creation of circuit and system blocks to realise this. The work culminates in the application challenges of developing a wireless RF front end, including antenna, for an Ultra Wideband communications systems applications. This thesis illustrates how higher levels of integration over the period of 1981 to 2010 have influenced the realisation of complex system level products, particularly analogue signal processing capabilities for communications applications. There have been many publications illustrating the impact of technology advancement from an economic or technology perspective. The thesis shows how technology advancement has impacted the physical realisation of semiconductor products over the period, at system, circuit, and physical implementation levels