4,602 research outputs found

    Equivalence Checking of Quantum Finite-State Machines

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    In this paper, we introduce the model of quantum Mealy machines and study the equivalence checking and minimisation problems of them. Two efficient algorithms are developed for checking equivalence of two states in the same machine and for checking equivalence of two machines. They are applied in experiments of equivalence checking of quantum circuits. Moreover, it is shown that the minimisation problem is proved to be in \textbf{PSPACE}

    Cross-level Validation of Topological Quantum Circuits

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    Quantum computing promises a new approach to solving difficult computational problems, and the quest of building a quantum computer has started. While the first attempts on construction were succesful, scalability has never been achieved, due to the inherent fragile nature of the quantum bits (qubits). From the multitude of approaches to achieve scalability topological quantum computing (TQC) is the most promising one, by being based on an flexible approach to error-correction and making use of the straightforward measurement-based computing technique. TQC circuits are defined within a large, uniform, 3-dimensional lattice of physical qubits produced by the hardware and the physical volume of this lattice directly relates to the resources required for computation. Circuit optimization may result in non-intuitive mismatches between circuit specification and implementation. In this paper we introduce the first method for cross-level validation of TQC circuits. The specification of the circuit is expressed based on the stabilizer formalism, and the stabilizer table is checked by mapping the topology on the physical qubit level, followed by quantum circuit simulation. Simulation results show that cross-level validation of error-corrected circuits is feasible.Comment: 12 Pages, 5 Figures. Comments Welcome. RC2014, Springer Lecture Notes on Computer Science (LNCS) 8507, pp. 189-200. Springer International Publishing, Switzerland (2014), Y. Shigeru and M.Shin-ichi (Eds.

    DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction

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    Recently much attention has been paid to quantum circuit design to prepare for the future "quantum computation era." Like the conventional logic synthesis, it should be important to verify and analyze the functionalities of generated quantum circuits. For that purpose, we propose an efficient verification method for quantum circuits under a practical restriction. Thanks to the restriction, we can introduce an efficient verification scheme based on decision diagrams called Decision Diagrams for Matrix Functions (DDMFs). Then, we show analytically the advantages of our approach based on DDMFs over the previous verification techniques. In order to introduce DDMFs, we also introduce new concepts, quantum functions and matrix functions, which may also be interesting and useful on their own for designing quantum circuits.Comment: 15 pages, 14 figures, to appear IEICE Trans. Fundamentals, Vol. E91-A, No.1

    Low Power Reversible Parallel Binary Adder/Subtractor

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    In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.Comment: 12 pages,VLSICS Journa

    Synthesis and Optimization of Reversible Circuits - A Survey

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    Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms --- search-based, cycle-based, transformation-based, and BDD-based --- as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table

    Graphical description of the action of Clifford operators on stabilizer states

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    We introduce a graphical representation of stabilizer states and translate the action of Clifford operators on stabilizer states into graph operations on the corresponding stabilizer-state graphs. Our stabilizer graphs are constructed of solid and hollow nodes, with (undirected) edges between nodes and with loops and signs attached to individual nodes. We find that local Clifford transformations are completely described in terms of local complementation on nodes and along edges, loop complementation, and change of node type or sign. Additionally, we show that a small set of equivalence rules generates all graphs corresponding to a given stabilizer state; we do this by constructing an efficient procedure for testing the equality of any two stabilizer graphs.Comment: 14 pages, 8 figures. Version 2 contains significant changes. Submitted to PR
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